An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors

Author(s):  
Chengyi Zhang ◽  
Hongwei Zhou ◽  
Minxuan Zhang ◽  
Zuocheng Xing
2012 ◽  
Vol 30 ◽  
pp. 1163-1170 ◽  
Author(s):  
M.Geetha Priya ◽  
K. Baskaran ◽  
D. Krishnaveni

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