Developing and Implementing IHPM on IXP 425 Network Processor Platforms

Information Security Applications - Lecture Notes in Computer Science ◽

10.1007/11604938_17 ◽

2006 ◽

pp. 218-231 ◽

Cited By ~ 1

Author(s):

Bo-Chao Cheng ◽

Ching-Fu Huang ◽

Wei-Chi Chang ◽

Cheng-Shong Wu

Keyword(s):

Network Processor

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Prioritized PWDEDF Scheduling Algorithm for QoS Enhancement using Network Processor

i-manager s Journal on Communication Engineering and Systems ◽

10.26634/jcs.3.1.2631 ◽

2014 ◽

Vol 3 (1) ◽

pp. 1-8

Author(s):

T. Anna Sudha ◽

Keyword(s):

Scheduling Algorithm ◽

Network Processor

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Transparent protocol translation and load balancing on a network processor in a media streaming scenario

Proceedings of the 18th International Workshop on Network and Operating Systems Support for Digital Audio and Video - NOSSDAV '08 ◽

10.1145/1496046.1496082 ◽

2008 ◽

Author(s):

Håvard Espeland ◽

Carl Henrik Lunde ◽

Håkon Kvale Stensland ◽

Carsten Griwodz ◽

Pål Halvorsen

Keyword(s):

Load Balancing ◽

Network Processor ◽

Media Streaming

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Architecture-Accuracy Co-optimization of ReRAM-based Low-cost Neural Network Processor

Proceedings of the 2020 on Great Lakes Symposium on VLSI ◽

10.1145/3386263.3406954 ◽

2020 ◽

Author(s):

Segi Lee ◽

Sugil Lee ◽

Jongeun Lee ◽

Jong-Moon Choi ◽

Do-Wan Kwon ◽

...

Keyword(s):

Neural Network ◽

Low Cost ◽

Network Processor

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Power delivery design and analysis on a network processor board

2004 International Symposium on Electromagnetic Compatibility (IEEE Cat. No.04CH37559) ◽

10.1109/isemc.2004.1350031 ◽

2004 ◽

Author(s):

W. Cui ◽

B. Aspnes ◽

P. Parmar ◽

M. Suryakumar

Keyword(s):

Network Processor ◽

Power Delivery ◽

Processor Board

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An efficient scheduling mechanism with flow-based packet reordering in a high-speed network processor

HPSR. 2005 Workshop on High Performance Switching and Routing, 2005. ◽

10.1109/hpsr.2005.1503279 ◽

2005 ◽

Author(s):

Beibei Wu ◽

Yang Xu ◽

Bin Liu ◽

Hongbin Lu ◽

Xiaojun Wang

Keyword(s):

High Speed ◽

Network Processor ◽

Packet Reordering ◽

High Speed Network

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The network processor decision

Bell Labs Technical Journal ◽

10.1002/bltj.20012 ◽

2004 ◽

Vol 9 (1) ◽

pp. 177-189 ◽

Cited By ~ 4

Author(s):

Michael Coss ◽

Ron Sharp

Keyword(s):

Network Processor

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Neural Network Processor for a FPGA-based Multiband Fluorometer Device

2006 International Workshop on Computer Architecture for Machine Perception and Sensing ◽

10.1109/camp.2007.4350381 ◽

2006 ◽

Author(s):

Karima Tabari ◽

Mounir Boukadoum ◽

Abdelhak Bensaoula ◽

David Starikov

Keyword(s):

Neural Network ◽

Network Processor

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Peak power reduction of a sensor network processor fabricated with Deeply Depleted Channel transistors in 65nm technology

International Symposium on Quality Electronic Design (ISQED) ◽

10.1109/isqed.2013.6523646 ◽

2013 ◽

Author(s):

K. Kawakami ◽

T. Shiro ◽

H. Yamasaki ◽

K. Yoda ◽

H. Fujimoto ◽

...

Keyword(s):

Sensor Network ◽

Peak Power ◽

Power Reduction ◽

Network Processor ◽

Peak Power Reduction

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Network Processor Performance Evaluation Framework

2006 International Conference on Communication Technology ◽

10.1109/icct.2006.342004 ◽

2006 ◽

Cited By ~ 2

Author(s):

Shan Zheng ◽

Zhao Rong-cai ◽

Xie Kang-min

Keyword(s):

Performance Evaluation ◽

Evaluation Framework ◽

Network Processor ◽

Processor Performance

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Neural network processor

10.1117/12.560815 ◽

2004 ◽

Author(s):

Michele R. Banish ◽

David B. Chenault ◽

John S. Harchanko

Keyword(s):

Neural Network ◽

Network Processor

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