scholarly journals IEEE 802.11e/802.11k wireless LAN: spectrum awareness for distributed resource sharing

2004 ◽  
Vol 4 (8) ◽  
pp. 881-902 ◽  
Author(s):  
Stefan Mangold ◽  
Zhun Zhong ◽  
Guido R. Hiertz ◽  
Bernhard Walke
Keyword(s):  
Resource Sharing ◽  
Wireless Lan ◽  
Ieee 802.11E

Medium access control access delay analysis of IEEE 802.11e wireless LAN

2009 ◽  
Vol 3 (6) ◽  
pp. 1061 ◽  
Author(s):  
W. Dapeng ◽  
Z. Yan ◽  
W. Muqing ◽  
Z. Xiaojing
Keyword(s):  
Access Control ◽  
Medium Access Control ◽  
Wireless Lan ◽  
Ieee 802.11E ◽  
Delay Analysis ◽  
Medium Access ◽  
Access Delay

scholarly journals Efficient Resource Sharing Architecture for Multistandard Communication System

VLSI Design ◽  
2011 ◽  
Vol 2011 ◽  
pp. 1-9 ◽  
Author(s):  
T. Suresh ◽  
K. L. Shunmuganathan
Keyword(s):  
Resource Sharing ◽  
Wireless Lan ◽  
Orthogonal Frequency Division Multiplexing ◽  
Dynamic Network ◽  
Hardware Architecture ◽  
Fourth Generation ◽  
Receiver Architecture ◽  
Efficient Resource ◽  
Code Division Multiple ◽  
Dedicated Hardware

The Fourth Generation (4G) network is expected to serve mobile subscribers under dynamic network conditions and offer any type service: anytime, anywhere, and anyhow. Two such technologies that can respond to the above said services are Wideband Code Division Multiple Access (WCDMA) and Orthogonal Frequency Division Multiplexing (OFDM). The main contribution of this paper is to propose a dedicated hardware module which can reconfigure itself either to the OFDM Wireless LAN or WCDMA standard. In this paper, Fast Fourier Transform (FFT) algorithm is implemented for OFDM standard, and rake receiver is implemented for WCDMA standard. Initially efficient implementations of these two algorithms are tested separately and identified the resources utilized by them. Then the new hardware architecture, which configures to any one of these two standards on demand, is proposed. This architecture efficiently shares the resources needed for these two standards. The proposed architecture is simulated using ModelSimSE v6.5 and mapped onto a virtex 5 FPGA device (xc5v1x30ff324) using the tool Xilinx ISE 9.2i, and the results are compared with the standard approach. These results show that the proposed hardware architecture utilizes less number of resources compared to the conventional Reconfigurable Receiver Architecture System.

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