Electric field measurement for quantum-dot cellular automata clocking circuits

2008 ◽  
Vol 40 (12) ◽  
pp. 1503-1506
Author(s):  
Minjun Yan
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Electric Field ◽  
Field Measurement ◽  
Electric Field Measurement ◽  
Quantum Dot Cellular Automata

scholarly journals Clock Topologies for Molecular Quantum-Dot Cellular Automata

2018 ◽  
Vol 8 (3) ◽  
pp. 31 ◽  
Author(s):  
Enrique Blair ◽  
Craig Lent
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Electric Field ◽  
General Purpose ◽  
Von Neumann ◽  
Quantum Dot Cellular Automata ◽  
A Cell ◽  
Charge Tunneling ◽  
Classical Computing ◽  
Planar Circuit

Quantum-dot cellular automata (QCA) is a low-power, non-von-Neumann, general-purpose paradigm for classical computing using transistor-free logic. Here, classical bits are encoded on the charge configuration of individual computing primitives known as “cells.” A cell is a system of quantum dots with a few mobile charges. Device switching occurs through quantum mechanical inter-dot charge tunneling, and devices are interconnected via the electrostatic field. QCA devices are implemented using arrays of QCA cells. A molecular implementation of QCA may support THz-scale clocking or better at room temperature. Molecular QCA may be clocked using an applied electric field, known as a clocking field. A time-varying clocking field may be established using an array of conductors. The clocking field determines the flow of data and calculations. Various arrangements of clocking conductors are laid out, and the resulting electric field is simulated. It is shown that that control of molecular QCA can enable feedback loops, memories, planar circuit crossings, and versatile circuit grids that support feedback and memory, as well as data flow in any of the ordinal grid directions. Logic, interconnect and memory now become indistinguishable, and the von Neumann bottleneck is avoided.

Improved Quantum Dot Cellular Automata 4:1 Multiplexer Circuit Unit

2014 ◽  
Vol 2014 (1) ◽  
pp. 37-44 ◽  
Author(s):  
Arighna Sarkar ◽  
◽  
Debarka Mukhopadhyay ◽  
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Quantum Dot Cellular Automata

Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata

2020 ◽  
Vol 10 (4) ◽  
pp. 534-547
Author(s):  
Chiradeep Mukherjee ◽  
Saradindu Panda ◽  
Asish K. Mukhopadhyay ◽  
Bansibadan Maji
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Digital Data ◽  
Design Parameters ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Cost Efficient

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.

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