P-158L:Late-News Poster: Development of A Silicon Process with Device Mobility >500 Cm2/V-Sec Suitable for a Large-Area Display Backplane Using Embedded Single-Crystal Silicon Particles

2015 ◽  
Vol 46 (1) ◽  
pp. 1334-1336 ◽  
Author(s):  
Feng Chen ◽  
Roohollah Samadzadeh Tarighat ◽  
Graham Hill ◽  
John Vieth ◽  
Siva Sivoththaman ◽  
...  
2014 ◽  
Vol 45 (1) ◽  
pp. 638-641 ◽  
Author(s):  
Douglas R. Dykaar ◽  
Behzad Esfandiarpour ◽  
Feng Chen ◽  
Simon Guthrie ◽  
Graham Hill ◽  
...  

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Yuki Tsuruma ◽  
Emi Kawashima ◽  
Yoshikazu Nagasaki ◽  
Takashi Sekiya ◽  
Gaku Imamura ◽  
...  

AbstractPower devices (PD) are ubiquitous elements of the modern electronics industry that must satisfy the rigorous and diverse demands for robust power conversion systems that are essential for emerging technologies including Internet of Things (IoT), mobile electronics, and wearable devices. However, conventional PDs based on “bulk” and “single-crystal” semiconductors require high temperature (> 1000 °C) fabrication processing and a thick (typically a few tens to 100 μm) drift layer, thereby preventing their applications to compact devices, where PDs must be fabricated on a heat sensitive and flexible substrate. Here we report next-generation PDs based on “thin-films” of “amorphous” oxide semiconductors with the performance exceeding the silicon limit (a theoretical limit for a PD based on bulk single-crystal silicon). The breakthrough was achieved by the creation of an ideal Schottky interface without Fermi-level pinning at the interface, resulting in low specific on-resistance Ron,sp (< 1 × 10–4 Ω cm2) and high breakdown voltage VBD (~ 100 V). To demonstrate the unprecedented capability of the amorphous thin-film oxide power devices (ATOPs), we successfully fabricated a prototype on a flexible polyimide film, which is not compatible with the fabrication process of bulk single-crystal devices. The ATOP will play a central role in the development of next generation advanced technologies where devices require large area fabrication on flexible substrates and three-dimensional integration.


2021 ◽  
Author(s):  
Yuki Tsuruma ◽  
Emi Kawashima ◽  
Yoshikazu Nagasaki ◽  
Takashi Sekiya ◽  
Gaku Imamura ◽  
...  

Abstract Power devices (PD) are ubiquitous elements of the modern electronics industry that must satisfy the rigorous and diverse demands for robust power conversion systems that are essential for emerging technologies including Internet of Things (IoT), mobile electronics, and wearable devices. However, conventional PDs based on “bulk” and “single-crystal” semiconductors require high temperature (>1000°C) fabrication processing and a thick (typically a few tens to 100 μm) drift layer1, thereby preventing their applications to compact devices2, where PDs must be fabricated on a heat sensitive and flexible substrate. Here we report next-generation PDs based on “thin-films” of “amorphous” oxide semiconductors with the performance exceeding the silicon limit (a theoretical limit for a PD based on bulk single-crystal silicon3). The breakthrough was achieved by the creation of an ideal Schottky interface without Fermi-level pinning at the interface, resulting in low specific on-resistance Ron,sp (<1×10-4 Ωcm2) and high breakdown voltage VBD (~100 V). To demonstrate the unprecedented capability of the amorphous thin-film oxide power devices (ATOPs), we successfully fabricated a prototype on a flexible polyimide film, which is not compatible with the fabrication process of bulk single-crystal devices. The ATOP will play a central role in the development of next generation advanced technologies where devices require large area fabrication on flexible substrates and three-dimensional integration.


2007 ◽  
Vol 40 (3) ◽  
pp. 489-495 ◽  
Author(s):  
M. Potter ◽  
H. Fritzsche ◽  
D. H. Ryan ◽  
L. M. D. Cranswick

Neutron diffraction measurements on weakly scattering or highly absorbing samples may demand custom mounting solutions. Two low-background sample holders based on inexpensive single-crystal silicon are described. One uses a conventional cylindrical geometry and is optimized for weakly scattering materials, while the other has a large-area flat-plate geometry and is designed for use with highly absorbing samples. Both holders yield much lower backgrounds than more conventional null-matrix or null-scattering materials and are essentially free from interfering Bragg peaks.


2008 ◽  
Vol 41 (1) ◽  
pp. 198-205 ◽  
Author(s):  
D. H. Ryan ◽  
L. M. D. Cranswick

The extreme absorption cross section of natural gadolinium has so far precluded routine neutron diffraction work on its alloys and compounds. However, it is shown here that an easily constructed flat-plate sample holder with silicon single-crystal windows can be used to place a thin layer of material in a neutron beam and obtain Rietveld refinement quality diffraction data in a modest time. The flat-plate geometry uses a large area to compensate for the necessarily thin sample. Demonstration data are presented on two intermetallic compounds, Sm3Ag4Sn4and Gd3Ag4Sn4, and it is shown that both structural and magnetic information can be derived from the diffraction patterns. By working at a wavelength of 2.37 Å, it is possible to observe the low-Qdiffraction peaks associated with magnetic ordering. This simple methodology should now enable routine measurements on even the most highly absorbing materials.


2011 ◽  
Vol 99 (22) ◽  
pp. 223105 ◽  
Author(s):  
Z. Y. Dang ◽  
M. Motapothula ◽  
Y. S. Ow ◽  
T. Venkatesan ◽  
M. B. H. Breese ◽  
...  

Nano Letters ◽  
2013 ◽  
Vol 13 (9) ◽  
pp. 4393-4398 ◽  
Author(s):  
Shuang Wang ◽  
Benjamin D. Weil ◽  
Yanbin Li ◽  
Ken Xingze Wang ◽  
Erik Garnett ◽  
...  

1985 ◽  
Vol 48 ◽  
Author(s):  
I. Golecki ◽  
R. L. Maddox ◽  
H. L. Glass ◽  
A. L. Lin ◽  
H. M. Manasevit

ABSTRACTA new approach to achieving a large-area silicon-on-insulator technology without pre-patterning is described. (100) Si films are first grown epitaxially on (100) yttria-stabilized cubic zirconia (YSZ) substrates by the pyrolysis of SiH4. The Si side of the <Si>/<YSZ>interface is then oxidized in pyrogenic steam (at 925 °C) or dry oxygen (at 1100°C) to form the structure <Si>/amorphous SiO2/<YSZ>. The oxidation occurs by the rapid diffusion of oxidants through the 0.42 mm thick YSZ substrate; e.g., a 0.3 μm SiO2 layer is obtained in 6 h in steam. The samples are analyzed by Rutherford backscattering and channeling spectrometry, X-ray diffraction, infra-red reflectance, Auger electron spectroscopy and sheet resistance measurements. In addition to forming the preferred Si/SiO2 interface, the back-side oxidation eliminates the most defective part of the Si film.


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