Affective response to different media in a multi-media system

1968 ◽  
Vol 52 (1) ◽  
pp. 16-22 ◽  
Author(s):  
M. Daniel Smith ◽  
Herbert J. Walberg ◽  
L. Eugene Poorman ◽  
Morton Schagrin
1969 ◽  
Vol 6 (4) ◽  
pp. 322-332
Author(s):  
M. Daniel Smith
Keyword(s):  

Author(s):  
Pengfei Li

Based on the current situation of the development of multi-media technology and its application in colleges and universities, this paper selected high-quality multi-media hardware devices suitable for the piano curriculum, followed Meyer’s principles for multi-media instruction design, and designed a multi-media through the visualization of multi-media information, promotion of necessary cognitive processing, reduction of external cognitive processing, stimulation of generative cognitive processing and other information processing methods, to improve the information presentation ways and delivery strategies for multi-media teaching software. To a certain extent, the system prevents teachers from neglecting learners’ cognitive mechanism when processing information for their multi-media teaching software, and also improves the multi-media teaching effect of music-oriented courses, thereby having important guiding significance for multi-media teaching as well as the design and production of teaching software. Meanwhile, it provides theoretical and statistical support for the application of high-quality multi-media teaching system in music-oriented courses and college education.


2012 ◽  
Vol 546-547 ◽  
pp. 469-474
Author(s):  
Xing Wang ◽  
Lei Bo Liu ◽  
Shou Yi Yin ◽  
Min Zhu ◽  
Shao Jun Wei

Coarse-Grained Reconfigurable Architectures (CGRA) have proved to be the potential candidates to meet the high performance, low power and flexibility required by embedded systems. In this paper, we implemented a High Profile Intra Predictor for H.264/AVC decoder on a novel coarse-grained reconfigurable processor- Remus (Reconfigurable Multi-media System). We proposed the pipeline and parallel scheduling process for intra prediction algorithm and the simulation results show that 548 clock cycles are consumed for the worst case of intra macro blocks.


Sign in / Sign up

Export Citation Format

Share Document