Nested and interleaved direct sequence spread spectrum to enhance CDMA security and bit error rate performance

2016 ◽  
Vol 29 (12) ◽  
pp. 1907-1915 ◽  
Author(s):  
Abolfazl Falahati ◽  
Nader Sanandaji

The digital communication technologies have gained immense significance as it provides secure and error free services. One of the major advantages of digital communication is that they are much resistant to transmitted as well as interpreted errors. For ensuring the security of data, the most suitable method is to use spread spectrum technique. The spread spectrum technique has gained immense popularity for use in various systems as the spreading of the spectral bandwidth offer many advantages, including the establishment of secure communications, increasing resistance to interference, noise rejection, and so on. The signals which are modulated by using these techniques cannot be jammed and are very hard to interfere. This paper presents the results of investigation of BPSK based direct sequence spread spectrum systems for Additive White Gaussian Noise (AWGN) and undersea channels. The bit error rate performance of BPSK based direct sequence spread spectrum systems has been simulated for the AWGN channel and the results have been plotted.


2013 ◽  
Vol 462-463 ◽  
pp. 896-899
Author(s):  
Ying Wang ◽  
Jiang Dong

Pulsed interference signal and pure frequency continuous wave (CW) jamming signal have the same effect on performance of bit error rate (BER). Due to equivalence, we can effectively simplify the complex of the direct sequence spread spectrum (DSSS) communication system. The equivalence will be simulated by the software SystemView in systematic level.


2010 ◽  
Vol 2 (6) ◽  
pp. 515-522
Author(s):  
Matthieu Gautier ◽  
Guillaume Villemaud ◽  
Ioan Burciu

In this paper, we address the architecture of a multi-antenna receiver and we aim at reducing the complexity of the analog front-end. To this end, an innovative architecture is introduced based on code multiplexing. This architecture uses the direct sequence spread spectrum technique in order to multiplex the different antennas contributions through a single In-phase/Quadrature (IQ) demodulator. Simulation and measurement results show that the bit error rate does not increase so much with the multiplexing in both Gaussian and fading environments and with strong radiofrequency (RF) defaults conditions. The complexity evaluation shows that the proposed architecture significantly reduces the chip area and the power consumption of the front-end.


2011 ◽  
Vol 103 ◽  
pp. 279-284 ◽  
Author(s):  
Xue Jun Li ◽  
Zhi Cheng He ◽  
Qi Li

This paper described the theory which based on the spread spectrum communication system, a simulation model was designed based on MATLAB, and each module of the model was briefly introduced. In a particular simulation condition, ran the simulation program, and an expected result was obtained. Meanwhile, by design a spread spectrum communication system of two users, detect the bit error rate corresponding with the two users in different bit error rate (SNR), directly verified the validity of the model system.


Author(s):  
Shinichi Watanabe ◽  
Minoru Okada

This paper proposes a simple positioning scheme without huge computational cost. The proposed scheme employs a three-element loop array for the transmitter. A Direct-Sequence Spread Spectrum (DS/SS) sequence is transmitted at a frequency of Low Frequency (LF) band. We evaluate location determination error rate by using a computer simulator and theoretical analysis. The theoretical analysis agrees with the simulation result. The difference is at most 1.3 dB at error rate of 10−5. Computer simulation result shows that the proposed technique can identify the region of 2 by 3 meters at the region determination error rate of 10−2. In order to show the hardware complexity requirement for implementing the proposed receiver, the impact of bit width for ADC (Analog-to-Digital Converter), and digital signal processing block to the error rate performance is evaluated by computer simulation. Computer simulation shows that the proposed scheme can be constructed by 2-bit ADC and 5-bit integrate and dump filter.


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