Substrate-thickness Dependence of Hydrogenated Microcrystalline Silicon Nucleation Rate on Amorphous Silicon Layer

2013 ◽  
Vol 19 (10-11-12) ◽  
pp. 363-366 ◽  
Author(s):  
Zewen Zuo ◽  
Guanglei Cui ◽  
Yu Wang ◽  
Junzhuan Wang ◽  
Lin Pu ◽  
...  
Keyword(s):  
Amorphous Silicon ◽  
Nucleation Rate ◽  
Silicon Layer ◽  
Thickness Dependence ◽  
Substrate Thickness ◽  
Microcrystalline Silicon

Effect of n doped amorphous layer between microcrystalline i/n layer on the performance of micromorph tandem solar cells

2015 ◽  
Vol 1771 ◽  
pp. 9-15
Author(s):  
Jingjing Yang ◽  
Tingkai Li ◽  
Xueshi Tan ◽  
Feng Zhang ◽  
Bingxue Mao
Keyword(s):  
Solar Cells ◽  
Amorphous Silicon ◽  
Silicon Layer ◽  
Chemical Vapor ◽  
Amorphous Layer ◽  
Microcrystalline Silicon ◽  
Tandem Solar Cells ◽  
Growth Defects ◽  
Vapor Deposition Technique ◽  
Silicon Growth

ABSTRACTPin/pin “micromorph” tandem solar cells were manufactured by the industrial production line of Hunan Gongchuang PV Science & Technology Co., Ltd. Based on this kind of solar cells, a n-doped amorphous silicon layer deposited by plasma enhanced chemical vapor deposition technique (PECVD) was inserted between the microcrystalline silicon intrinsic layer and n-doped layer. The result showed that the introduced n-type amorphous silicon layer well improved the solar cells performance by reducing the bad effects caused by microcrystalline silicon growth defects. Compared with the solar cells without inserting the n-doped amorphous silicon layer, the open voltage and efficiency increased remarkably. When the thickness of n-doped amorphous silicon layer is 8nm, the open voltage increased from 72.9V to 73.6V and efficiency increased from 10.63% to 10.74%.

High Temperature n- and p-type Doped Microcrystalline Silicon Layers Grown by VHF PECVD Layer-by-Layer Deposition

2003 ◽  
Vol 762 ◽  
Author(s):  
A. Gordijn ◽  
J.K. Rath ◽  
R.E.I. Schropp
Keyword(s):  
Activation Energy ◽  
High Temperature ◽  
High Temperatures ◽  
Continuous Wave ◽  
Hydrogen Plasma ◽  
Silicon Layer ◽  
Dark Conductivity ◽  
High Deposition Rate ◽  
Layer By Layer ◽  
Microcrystalline Silicon

AbstractDue to the high temperatures used for high deposition rate microcrystalline (μc-Si:H) and polycrystalline silicon, there is a need for compact and temperature-stable doped layers. In this study we report on films grown by the layer-by-layer method (LbL) using VHF PECVD. Growth of an amorphous silicon layer is alternated by a hydrogen plasma treatment. In LbL, the surface reactions are separated time-wise from the nucleation in the bulk. We observed that it is possible to incorporate dopant atoms in the layer, without disturbing the nucleation. Even at high substrate temperatures (up to 400°C) doped layers can be made microcrystalline. At these temperatures, in the continuous wave case, crystallinity is hindered, which is generally attributed to the out-diffusion of hydrogen from the surface and the presence of impurities (dopants).We observe that the parameter window for the treatment time for p-layers is smaller compared to n-layers. Moreover we observe that for high temperatures, the nucleation of p-layers is more adversely affected than for n-layers. Thin, doped layers have been structurally, optically and electrically characterized. The best n-layer made at 400°C, with a thickness of only 31 nm, had an activation energy of 0.056 eV and a dark conductivity of 2.7 S/cm, while the best p-layer made at 350°C, with a thickness of 29 nm, had an activation energy of 0.11 V and a dark conductivity of 0.1 S/cm. The suitability of these high temperature n-layers has been demonstrated in an n-i-p microcrystalline silicon solar cell with an unoptimized μc-Si:H i-layer deposited at 250°C and without buffer. The Voc of the cell is 0.48 V and the fill factor is 70 %.

p-type nc-SiOx:H emitter layer for silicon heterojunction solar cells grown by rf-PECVD

2015 ◽  
Vol 1770 ◽  
pp. 7-12 ◽  
Author(s):  
Henriette A. Gatz ◽  
Yinghuan Kuang ◽  
Marcel A. Verheijen ◽  
Jatin K. Rath ◽  
Wilhelmus M.M. (Erwin) Kessels ◽  
...  
Keyword(s):  
Solar Cells ◽  
Amorphous Silicon ◽  
Material Properties ◽  
Crystalline Silicon ◽  
Silicon Layer ◽  
Nanocrystalline Silicon ◽  
Emitter Layer ◽  
Heterojunction Solar Cells ◽  
P Type ◽  
Silicon Heterojunction Solar Cells

ABSTRACTSilicon heterojunction solar cells (SHJ) with thin intrinsic layers are well known for their high efficiencies. A promising way to further enhance their excellent characteristics is to enable more light to enter the crystalline silicon (c-Si) absorber of the cell while maintaining a simple cell configuration. Our approach is to replace the amorphous silicon (a-Si:H) emitter layer with a more transparent nanocrystalline silicon oxide (nc-SiOx:H) layer. In this work, we focus on optimizing the p-type nc-SiOx:H material properties, grown by radio frequency plasma enhanced chemical vapor deposition (rf PECVD), on an amorphous silicon layer.20 nm thick nanocrystalline layers were successfully grown on a 5 nm a-Si:H layer. The effect of different ratios of trimethylboron to silane gas flow rates on the material properties were investigated, yielding an optimized material with a conductivity in the lateral direction of 7.9×10-4 S/cm combined with a band gap of E04 = 2.33 eV. Despite its larger thickness as compared to a conventional window a-Si:H p-layer, the novel layer stack of a-Si:H(i)/nc-SiOx:H(p) shows significantly enhanced transmission compared to the stack with a conventional a-Si:H(p) emitter. Altogether, the chosen material exhibits promising characteristics for implementation in SHJ solar cells.

Study on Light Induced Leakage Current Related to Amorphous Silicon TFT Design

2007 ◽  
Vol 124-126 ◽  
pp. 259-262
Author(s):  
Jae Hong Jeon ◽  
Kang Woong Lee
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Leakage Current ◽  
Thin Film Transistor ◽  
Silicon Layer ◽  
Gate Electrode ◽  
Silicon Thin Film ◽  
Pattern Design ◽  
Conventional Design ◽  
The One

We investigated the effect of amorphous silicon pattern design regarding to light induced leakage current in amorphous silicon thin film transistor. In addition to conventional design, where amorphous silicon layer is protruding outside the gate electrode, we designed and fabricated amorphous silicon thin film transistors in another two types of bottom gated structure. The one is that the amorphous silicon layer is located completely inside the gate electrode and the other is that the amorphous silicon layer is protruding outside the gate electrode but covered completely by the source and drain electrode. Measurement of the light induced leakage current caused by backlight revealed that the design where the amorphous silicon is located inside the gate electrode was the most effective however the last design was also effective in reducing the leakage current about one order lower than that of the conventional design.

Mesotaxy by nickel diffusion into a buried amorphous silicon layer

1992 ◽  
Vol 12 (1-2) ◽  
pp. 103-106 ◽  
Author(s):  
Yu.N. Erokhin ◽  
R. Grötzschel ◽  
S.R. Oktyabrsky ◽  
S. Roorda ◽  
W. Sinke ◽  
...  
Keyword(s):  
Amorphous Silicon ◽  
Silicon Layer
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