A low-power small-area 10-bit analog-to-digital converter for neural recording applications

2011 ◽  
Vol 39 (4) ◽  
pp. 385-395 ◽  
Author(s):  
Mohammad Hossein Zarifi ◽  
Javad Frounchi ◽  
Mohammad Ali Tinati ◽  
Shahin Farshchi ◽  
Jack W. Judy
Keyword(s):  
Low Power ◽  
Small Area ◽  
Neural Recording ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital

scholarly journals A Design of a New Column-Parallel Analog-to-Digital Converter Flash for Monolithic Active Pixel Sensor

2017 ◽  
Vol 2017 ◽  
pp. 1-15 ◽  
Author(s):  
Mostafa Chakir ◽  
Hicham Akhamal ◽  
Hassan Qjidaa
Keyword(s):  
Low Power ◽  
Input Signal ◽  
Small Area ◽  
High Speed ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Active Pixel Sensor ◽  
Analog To Digital ◽  
Active Pixel ◽  
5 Ghz

The CMOS Monolithic Active Pixel Sensor (MAPS) for the International Linear Collider (ILC) vertex detector (VXD) expresses stringent requirements on their analog readout electronics, specifically on the analog-to-digital converter (ADC). This paper concerns designing and optimizing a new architecture of a low power, high speed, and small-area 4-bit column-parallel ADC Flash. Later in this study, we propose to interpose an S/H block in the converter. This integration of S/H block increases the sensitiveness of the converter to the very small amplitude of the input signal from the sensor and provides a sufficient time to the converter to be able to code the input signal. This ADC is developed in 0.18 μm CMOS process with a pixel pitch of 35 μm. The proposed ADC responds to the constraints of power dissipation, size, and speed for the MAPS composed of a matrix of 64 rows and 48 columns where each column ADC covers a small area of 35 × 336.76 μm2. The proposed ADC consumes low power at a 1.8 V supply and 100 MS/s sampling rate with dynamic range of 125 mV. Its DNL and INL are 0.0812/−0.0787 LSB and 0.0811/−0.0787 LSB, respectively. Furthermore, this ADC achieves a high speed more than 5 GHz.

scholarly journals Ein 10 bit 10MS/s Low-Power AD-Converter in 0.11mm2

2005 ◽  
Vol 2 ◽  
pp. 205-209
Author(s):  
D. Muthers ◽  
R. Tielert
Keyword(s):  
Low Power ◽  
Small Area ◽  
Digital Filters ◽  
Cmos Process ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Mixed Signal ◽  
Analog To Digital ◽  
Ad Converter ◽  
Mim Capacitors

Abstract. Ein 10 bit 10MS/s Analog-Digital- Wandler mit niedriger Leistungaufnahme von 8,4mW wurde implementiert. Der geringe Flächenbedarf von 0,11mm2 macht diesen Wandler besonders geeignet f¨ur Multikanalanwendungen. Um die Anforderungen von 10 bit, 10 MS/s möglichst effizient zu erfüllen wurde eine zyklische Wandlerarchitektur gewählt, die in einem 0,18μm-CMOSProzess mit MIM-Kondensatoren implementiert wurde. Der entworfene ADC wurde in 21 parallelen Kanälen auf einem mixed-signal-Chip zusammen mit digitalen Filtern, vier RISC-CPUs und I/O-Schaltungen implementiert. A 10 bit 10MS/s Analog to Digital Converter, consuming a power of 8,4mW, has been implemented. Due to the small area of 0,11mm2 this ADC is highly suited for multichannel implementations. A cyclic converter architecture is best suited for this application, being implemented in a 0,18μm CMOS process with MIM-capacitors. The designed ADC was implemented in an array of 21 channels on a mixed signal chip together with digital filters, four RISC-CPUs and I/O circuitry.

A novel time-based low-power pipeline analog to digital converter

2009 ◽  
Vol 62 (3) ◽  
pp. 281-289 ◽  
Author(s):  
Mohammad Hossein Zarifi ◽  
Javad Frounchi ◽  
Shahin Farshchi ◽  
Jack W. Judy
Keyword(s):  
Low Power ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital
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