Efficient memory architecture for image processing

Stefania Perri; Pasquale Corsonello

doi:10.1002/cta.625

Efficient memory architecture for image processing

International Journal of Circuit Theory and Applications ◽

10.1002/cta.625 ◽

2011 ◽

Vol 39 (3) ◽

pp. 351-356 ◽

Cited By ~ 9

Author(s):

Stefania Perri ◽

Pasquale Corsonello

Keyword(s):

Image Processing ◽

Memory Architecture ◽

Efficient Memory

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Visual Image Processing RAM: Memory Architecture With 2-D Data Location Search and Data Consistency Management for a Multicore Object Recognition Processor

IEEE Transactions on Circuits and Systems for Video Technology ◽

10.1109/tcsvt.2009.2035830 ◽

2010 ◽

Vol 20 (4) ◽

pp. 485-495 ◽

Cited By ~ 5

Author(s):

Joo-Young Kim ◽

Donghyun Kim ◽

Seungjin Lee ◽

Kwanho Kim ◽

Hoi-Jun Yoo

Keyword(s):

Image Processing ◽

Object Recognition ◽

Visual Image ◽

Data Consistency ◽

Memory Architecture ◽

Consistency Management ◽

Data Location

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Three-dimensional image processing VLSI system with network-on-chip system and reconfigurable memory architecture

IEEE Transactions on Consumer Electronics ◽

10.1109/tce.2011.6018893 ◽

2011 ◽

Vol 57 (3) ◽

pp. 1345-1353 ◽

Cited By ~ 2

Author(s):

Yun Yang

Keyword(s):

Image Processing ◽

Three Dimensional ◽

Network On Chip ◽

Memory Architecture ◽

Dimensional Image ◽

Vlsi System ◽

Reconfigurable Memory ◽

On Chip

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Energy Efficient Memory Architecture for High Speed Decoding of Block Turbo-Codes with the Fang-Buda Algorithm

The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology ◽

10.1023/b:vlsi.0000047273.61038.18 ◽

2005 ◽

Vol 39 (1/2) ◽

pp. 79-92

Author(s):

B. Bougard ◽

M. Rullmann ◽

E. Brockmeyer ◽

L. van der Perre ◽

F. Catthoor ◽

...

Keyword(s):

Turbo Codes ◽

Energy Efficient ◽

High Speed ◽

Memory Architecture ◽

Efficient Memory ◽

Block Turbo Codes

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IPStash: a power-efficient memory architecture for IP-lookup

22nd Digital Avionics Systems Conference Proceedings (Cat No 03CH37449) MICRO-03 ◽

10.1109/micro.2003.1253210 ◽

2004 ◽

Cited By ~ 14

Author(s):

S. Kaxiras ◽

G. Keramidas

Keyword(s):

Memory Architecture ◽

Power Efficient ◽

Ip Lookup ◽

Efficient Memory

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A distributed memory architecture for morphological image processing

Proceedings ITCC 2003. International Conference on Information Technology: Coding and Computing ◽

10.1109/itcc.2003.1197586 ◽

2004 ◽

Cited By ~ 1

Author(s):

A.D. Kishore ◽

S. Srinivasan

Keyword(s):

Image Processing ◽

Distributed Memory ◽

Memory Architecture ◽

Morphological Image Processing ◽

Morphological Image ◽

Distributed Memory Architecture

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New Reconfigurable Memory Architecture for Parallel Image-Processing LSI with Three-Dimensional Structure

Japanese Journal of Applied Physics ◽

10.1143/jjap.47.2774 ◽

2008 ◽

Vol 47 (4) ◽

pp. 2774-2778 ◽

Cited By ~ 4

Author(s):

Shigeo Kodama ◽

Daijirou Amano ◽

Takeaki Sugimura ◽

Takafumi Fukushima ◽

Tetsu Tanaka ◽

...

Keyword(s):

Image Processing ◽

Three Dimensional ◽

Dimensional Structure ◽

Memory Architecture ◽

Three Dimensional Structure ◽

Parallel Image Processing ◽

Parallel Image ◽

Reconfigurable Memory

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A high efficient memory architecture for H.264/AVC motion compensation

ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors ◽

10.1109/asap.2010.5540963 ◽

2010 ◽

Cited By ~ 2

Author(s):

Chunshu Li ◽

Kai Huang ◽

Xiaolang Yan ◽

Jiong Feng ◽

De Ma ◽

...

Keyword(s):

Motion Compensation ◽

Memory Architecture ◽

High Efficient ◽

Efficient Memory

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Novel parallel Givens QR decomposition implementation on VLIW architecture with Efficient memory access for real time image processing applications

Proceedings of the 2nd international Conference on Big Data, Cloud and Applications ◽

10.1145/3090354.3090445 ◽

2017 ◽

Cited By ~ 1

Author(s):

Mohamed Najoui ◽

Anas Hatim ◽

Said Belkouch

Keyword(s):

Image Processing ◽

Real Time ◽

Qr Decomposition ◽

Memory Access ◽

Real Time Image Processing ◽

Real Time Image ◽

Efficient Memory ◽

Time Image

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Three-dimensional image processing VLSI system with reconfigurable memory architecture and RAM/ROM synthesis design

2011 IEEE 9th International New Circuits and systems conference ◽

10.1109/newcas.2011.5981273 ◽

2011 ◽

Author(s):

Yun Yang

Keyword(s):

Image Processing ◽

Three Dimensional ◽

Memory Architecture ◽

Dimensional Image ◽

Synthesis Design ◽

Vlsi System ◽

Reconfigurable Memory

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New Reconfigurable Memory Architecture for Parallel Image Processing LSI with Three-Dimensional Structure

10.7567/ssdm.2007.g-9-4 ◽

2007 ◽

Author(s):

Shigeo Kodama ◽

Daijiro Amano ◽

Takeaki Sugimura ◽

Takafumi Fukushima ◽

Tetsu Tanaka ◽

...

Keyword(s):

Image Processing ◽

Three Dimensional ◽

Dimensional Structure ◽

Memory Architecture ◽

Three Dimensional Structure ◽

Parallel Image Processing ◽

Parallel Image ◽

Reconfigurable Memory

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