Design and investigation of a triple boost multilevel inverter with self‐balanced switched capacitors and reduced voltage stress

Author(s):  
Zeeshan Sarwer ◽  
Md Nishat Anwar ◽  
Adil Sarwar
Author(s):  
Liju Shaji ◽  
Praveen Bansal

In this paper, a new 9-level inverter employing switched capacitor technique is proposed. Three bidirectional voltage blocking switches are employed to connect the four H-bridges and to incorporate the three switched capacitors. The proposed multilevel inverter (MLI) circuit outputs a 9-level waveform with a maximum boosting factor of four. Unlike the already established switched capacitor based MLI consisting of two stages the proposed MLI is single stage inverter. The switches in the proposed MLI is subjected to a low value of voltage stress equal to Vdc. The proposed MLI is further analyzed by using various multicarrier sinusoidal PWM technique such as Phase Shift PWM (PSPWM), Phase disposition PWM (PDPWM), Phase Opposition Disposition PWM (PODPWM), Alternate Phase Opposition Disposition PWM (APODPWM) and Variable Frequency PWM (VFPWM).


Author(s):  
Abhinandan Routray ◽  
Kharan Shiluveru ◽  
Akash Singh ◽  
Rajeev Kumar Singh ◽  
Ranjit Mahanty

2019 ◽  
Vol 29 (08) ◽  
pp. 2050117
Author(s):  
Madan Kumar Das ◽  
Akanksha Sinha ◽  
Kartick Chandra Jana

A novel asymmetrical nine-level inverter topology using only six switches along with its generalized structure are presented in this paper. The proposed reduced switch multilevel inverter topology makes use of a lower total standing voltage for a required output voltage as compared to the existing ones. One of the major advantages of the proposed multilevel inverter over other existing topologies is that, the circuit can be extended to a higher-level inverter, by cascading a few proposed inverter modules and can also be extended to the three-phase structure very easily, thereby making the inverter structure simple. In addition to this, the proposed inverter module does not require any additional H-bridge circuit to obtain the negative voltage levels for AC voltage, resulting in reduced voltage stress on the switches. This paper also incorporates an effective technique to determine the total standing voltage as well as the switching and conduction losses of the inverter. The MATLAB/Simulink based proposed nine-level as well as an 81-level inverters are modeled and the simulation results are presented. An experimental prototype of nine-level inverter using six switches is developed and tested to validate the simulation results.


IEEE Access ◽  
2020 ◽  
Vol 8 ◽  
pp. 201835-201846
Author(s):  
Marif Daula Siddique ◽  
Saad Mekhilef ◽  
Muhyaddin Rawa ◽  
Addy Wahyudie ◽  
Bekkhan Chokaev ◽  
...  

Author(s):  
Kennedy Aganah ◽  
Cristopher Luciano ◽  
Mandoye Ndoye ◽  
Gregory Murphy

The past two decades has seen a growing demand for high-power, high-voltage utility scale inverters mostly fueled by the integration of large solar PV and wind farms. Multilevel inverters have emerged as the industry choice for these megawatt range inverters because their reduced voltage stress, capable of generating an almost sinusoidal voltage, in-built redundancy, among others. This paper present a new Switched-Source Multilevel Inverter (SS MLI) architecture. The new inverter show superior over existing topologies. It has reduced voltage stress on the semiconductor, uses less number of switches –reduced size/weight/cost and increased efficiency. The new SSMLI is comprised of two voltage sources (V1, V2) and 6 switches. It is capable of generating 5-level output voltage in symmetric modes (i.e., V1 = V2), and 7-level output voltage in asymmetric modes (i.e., V1 ≠ V2). To demonstrate the validity of the proposed inverter, simulations results using MATLAB® /Simulink® for 5- and 7-level output voltages are presented . The simulations are also verified experimentally using a laboratory prototype.


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