A single-bit continuous-time delta-sigma modulator using clock-jitter and inter-symbol-interference suppression technique

2016 ◽  
Vol 45 (1) ◽  
pp. 63-82 ◽  
Author(s):  
Vahid Sabouhi ◽  
Esmaeil Najafi Aghdam ◽  
Saeed Saeedi
Keyword(s):  
Continuous Time ◽  
Interference Suppression ◽  
Clock Jitter ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Suppression Technique ◽  
Inter Symbol Interference

A continuous time delta-sigma modulator with reduced clock jitter sensitivity through DSCR feedback

2012 ◽  
Vol 74 (1) ◽  
pp. 21-31 ◽  
Author(s):  
Dejan Radjen ◽  
Pietro Andreani ◽  
Martin Anderson ◽  
Lars Sundström
Keyword(s):  
Continuous Time ◽  
Clock Jitter ◽  
Delta Sigma Modulator ◽  
Delta Sigma

A Wideband Continuous Time Quadrature Delta Sigma Modulator Based on a Real DSM for Low Power WLAN Receiver

2017 ◽  
Vol 27 (03) ◽  
pp. 1850044 ◽  
Author(s):  
Alireza Shamsi ◽  
Esmaeil Najafi Aghdam
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Continuous Time ◽  
Signal To Noise Ratio ◽  
System Level ◽  
Complex Coefficient ◽  
Loop Filter ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Excess Loop Delay

Power consumption and bandwidth are two of the most important parameters in design of low power wideband modulators as power consumption is growing with the increase in bandwidth. In this study, a multi bit wideband low-power continuous time feed forward quadrature delta sigma modulator (CT-FF-QDSM) is designed for WLAN receiver applications by eliminating adders from modulator structure. In this method, a real modulator is designed and its excess loop delay (ELD) is compensated, then, it is converted into a quadrature structure by applying the complex coefficient to loop filter. Complex coefficients are extracted by the aid of a genetic algorithm to further improve signal to noise ratio (SNR) for bandwidth. One of the disadvantages of CT-FF-QDSM is the adders of loop filters which are power hungry and reduce the effective loop gain. Therefore, the adders have been eliminated while the transfer function is intact in the final modulator. The system level SNR of the proposed modulator is 62.53[Formula: see text]dB using OSR of 12. The circuit is implemented in CMOSTSMC180nm technology. The circuit levels SNR and power consumption are 54[Formula: see text]dB and 13.5[Formula: see text]mW, respectively. Figure of Merit (FOM) obtained from the proposed modulator is about 0.824 (pj/conv) which is improved (by more than 40%) compared to the previous designs.

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