A Review on Dielectric Breakdown in Thin Dielectrics: Silicon Dioxide, High‐ k , and Layered Dielectrics

2019 ◽  
Vol 30 (18) ◽  
pp. 1900657 ◽  
Author(s):  
Felix Palumbo ◽  
Chao Wen ◽  
Salvatore Lombardo ◽  
Sebastian Pazos ◽  
Fernando Aguirre ◽  
...  
Keyword(s):  
Silicon Dioxide ◽  
Dielectric Breakdown ◽  
High K ◽  
Layered Dielectrics ◽  
Thin Dielectrics

Design and Analysis of a Dual-Step Field-Plate Terminated 4H-SiC Schottky Diode Using SiO2/High-K Dielectric Stack

2006 ◽  
Vol 527-529 ◽  
pp. 1171-1174 ◽  
Author(s):  
A. Kumta ◽  
E. Rusli ◽  
Chin Che Tin
Keyword(s):  
Dielectric Constant ◽  
Silicon Dioxide ◽  
Breakdown Voltage ◽  
Dielectric Breakdown ◽  
Schottky Diodes ◽  
Single Step ◽  
Field Plate ◽  
Lower Dielectric Constant ◽  
High K ◽  
High K Dielectric

Silicon carbide (SiC) field plate terminated Schottky diodes using silicon dioxide (Si02) dielectric experience high electric field in the insulator and premature dielectric breakdown, attributed to the lower dielectric constant of the oxide. This problem can be addressed by using high-k dielectrics such as silicon nitride (Si3N4) that will reduce the field, increase the breakdown voltage and consequently improve the lifetime of the devices. While the advantages of single step field-plate terminated diodes are well-known, the breakdown voltage can be improved even further using a dual-step field-plate termination. Our 2D-numerical simulations using MEDICI have shown an improvement in breakdown voltages in excess of 25% compared to the traditional single-step field-plate terminated diodes.

Reliability of Metal Gate / High-k devices and its impact on CMOS technology scaling

MRS Advances ◽  
2017 ◽  
Vol 2 (52) ◽  
pp. 2973-2982 ◽  
Author(s):  
Andreas Kerber
Keyword(s):  
Dielectric Breakdown ◽  
Cmos Technology ◽  
Gate Stack ◽  
Leakage Currents ◽  
Technology Scaling ◽  
Device Scaling ◽  
Novel Device ◽  
Time Dependent Dielectric Breakdown ◽  
Bias Temperature Instability ◽  
High K

ABSTRACTMG/HK was introduced into CMOS technology and enabled scaling beyond the 45/32nm technology node. The change in gate stack from poly-Si/SiON to MG/HK introduced new reliability challenges like the positive bias temperature instability (PBTI) and stress induced leakage currents (SILC) in nFET devices which prompted thorough investigation to provide fundamental understanding of these degradation mechanisms and are nowadays well understood. The shift to a dual-layer gate stack also had a profound impact on the time dependent dielectric breakdown (TDDB) introducing a strong polarity dependence in the model parameter. As device scaling continues, stochastic modeling of variability, both at time zero and post stress due to BTI, becomes critical especially for SRAM circuit aging. As we migrate towards novel device architectures like bulk FinFET, SOI FinFETs, FDSOI and gate-all-around devices, impact of self-heating needs to be accounted for in reliability testing.In this paper we summarize the fundamentals of MG/HK reliability and discuss the reliability and characterization challenges related to the scaling of future CMOS technologies.

scholarly journals Peculiarities of time-dependent-dielectric breakdown characteristics of pure and doped Ta2O5 stacks

2013 ◽  
Vol 26 (3) ◽  
pp. 281-296
Author(s):  
E. Atanassova ◽  
A. Paskaleva
Keyword(s):  
Dielectric Breakdown ◽  
Interface Layer ◽  
Time Dependent ◽  
Relative Impact ◽  
Time Dependent Dielectric Breakdown ◽  
Breakdown Mechanism ◽  
Number Of Factors ◽  
High K ◽  
Induced Defects

The effect of both the process-induced defects and the dopant on the time-dependent-dielectric breakdown in Ta2O5 stacks is discussed. The breakdown degradation is analyzed in terms of specific properties of high-k stacks which make their dielectric breakdown mechanism completely different from that of classical SiO2. The relative impact of a number of factors constituting the reliability issues in Ta2O5-based capacitors (trapping in pre-existing traps, stress-induced new traps generation, the presence of interface layer at Si and the role of the dopant) is clarified.

Nanometer Resolution Measurement of Dielectric Breakdown of Silicon Dioxide Films with AFM/STM

1992 ◽  
Author(s):  
Yoshinobu FUKANO ◽  
Yasuhiro SUGAWARA ◽  
Seizo MORITA ◽  
Yoshiki YAMANISHI ◽  
Takahiko OASA
Keyword(s):  
Silicon Dioxide ◽  
Dielectric Breakdown ◽  
Nanometer Resolution ◽  
Resolution Measurement ◽  
Silicon Dioxide Films
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