scholarly journals SelectDirectory: A Selective Directory for Cache Coherence in Many-Core Architectures

2015 ◽  
Author(s):  
Yuan Yao ◽  
Guanhua Wang ◽  
Zhiguo Ge ◽  
Tulika Mitra ◽  
Wenzhi Chen ◽  
...  
Keyword(s):  
Cache Coherence ◽  
Many Core

A Novel Hybrid Cache Coherence with Global Snooping for Many-core Architectures

2022 ◽  
Vol 27 (1) ◽  
pp. 1-31
Author(s):  
Sri Harsha Gade ◽  
Sujay Deb
Keyword(s):  
Lower Energy ◽  
Cache Coherence ◽  
Network On Chip ◽  
Highly Efficient ◽  
Wireless Links ◽  
Coherence Protocols ◽  
High Area ◽  
On Chip ◽  
Many Core ◽  
Clustered Network

Cache coherence ensures correctness of cached data in multi-core processors. Traditional implementations of existing protocols make them unscalable for many core architectures. While snoopy coherence requires unscalable ordered networks, directory coherence is weighed down by high area and energy overheads. In this work, we propose Wireless-enabled Share-aware Hybrid (WiSH) to provide scalable coherence in many core processors. WiSH implements a novel Snoopy over Directory protocol using on-chip wireless links and hierarchical, clustered Network-on-Chip to achieve low-overhead and highly efficient coherence. A local directory protocol maintains coherence within a cluster of cores, while coherence among such clusters is achieved through global snoopy protocol. The ordered network for global snooping is provided through low-latency and low-energy broadcast wireless links. The overheads are further reduced through share-aware cache segmentation to eliminate coherence for private blocks. Evaluations show that WiSH reduces traffic by and runtime by , while requiring smaller storage and lower energy as compared to existing hierarchical and hybrid coherence protocols. Owing to its modularity, WiSH provides highly efficient and scalable coherence for many core processors.

Architecture and Evaluation of Low Power Many-Core SoC with Two 32-Core Clusters

2014 ◽  
Vol E97.C (4) ◽  
pp. 360-368
Author(s):  
Takashi MIYAMORI ◽  
Hui XU ◽  
Hiroyuki USUI ◽  
Soichiro HOSODA ◽  
Toru SANO ◽  
...  
Keyword(s):  
Low Power ◽  
Many Core

On Synchronization and Evaluation Method of Chipped Many-Core Processor

2010 ◽  
Vol 33 (10) ◽  
pp. 1777-1787 ◽  
Author(s):  
Wei-Zhi XU ◽  
Feng-Long SONG ◽  
Zhi-Yong LIU ◽  
Dong-Rui FAN ◽  
Lei YU ◽  
...  
Keyword(s):  
Evaluation Method ◽  
Many Core
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