scholarly journals Data Mining MPSoC Simulation Traces to Identify Concurrent Memory Access Patterns

2013 ◽  
Author(s):  
Sofiane Lagraa ◽  
Alexandre Termier ◽  
Frederic Petrot
Keyword(s):  
Data Mining ◽  
Memory Access ◽  
Access Patterns

EFFECTIVENESS OF COMPILER-DIRECTED PREFETCHING ON DATA MINING BENCHMARKS

2012 ◽  
Vol 21 (02) ◽  
pp. 1240006 ◽  
Author(s):  
RAGAVENDRA NATARAJAN ◽  
VINEETH MEKKAT ◽  
WEI-CHUNG HSU ◽  
ANTONIA ZHAI
Keyword(s):  
Data Mining ◽  
Dynamic Performance ◽  
Control Flow ◽  
Memory Access ◽  
Performance Tuning ◽  
Multicore Systems ◽  
Long Latency ◽  
Memory Accesses ◽  
Access Patterns ◽  
Level Parallelism

For today's increasingly power-constrained multicore systems, integrating simpler and more energy-efficient in-order cores becomes attractive. However, since in-order processors lack complex hardware support for tolerating long-latency memory accesses, developing compiler technologies to hide such latencies becomes critical. Compiler-directed prefetching has been demonstrated effective on some applications. On the application side, a large class of data centric applications has emerged to explore the underlying properties of the explosively growing data. These applications, in contrast to traditional benchmarks, are characterized by substantial thread-level parallelism, complex and unpredictable control flow, as well as intensive and irregular memory access patterns. These applications are expected to be the dominating workloads on future microprocessors. Thus, in this paper, we investigated the effectiveness of compiler-directed prefetching on data mining applications in in-order multicore systems. Our study reveals that although properly inserted prefetch instructions can often effectively reduce memory access latencies for data mining applications, the compiler is not always able to exploit this potential. Compiler-directed prefetching can become inefficient in the presence of complex control flow and memory access patterns; and architecture dependent behaviors. The integration of multithreaded execution onto a single die makes it even more difficult for the compiler to insert prefetch instructions, since optimizations that are effective for single-threaded execution may or may not be effective in multithreaded execution. Thus, compiler-directed prefetching must be judiciously deployed to avoid creating performance bottlenecks that otherwise do not exist. Our experiences suggest that dynamic performance tuning techniques that adjust to the behaviors of a program can potentially facilitate the deployment of aggressive optimizations in data mining applications.

scholarly journals Understanding memory access patterns using the BSC performance tools

2018 ◽  
Vol 78 ◽  
pp. 1-14 ◽  
Author(s):  
Harald Servat ◽  
Jesús Labarta ◽  
Hans-Christian Hoppe ◽  
Judit Giménez ◽  
Antonio J. Peña
Keyword(s):  
Memory Access ◽  
Access Patterns

scholarly journals An Efficient GPU Cache Architecture for Applications with Irregular Memory Access Patterns

2019 ◽  
Vol 16 (3) ◽  
pp. 1-24
Author(s):  
Bingchao Li ◽  
Jizeng Wei ◽  
Jizhou Sun ◽  
Murali Annavaram ◽  
Nam Sung Kim
Keyword(s):  
Memory Access ◽  
Cache Architecture ◽  
Access Patterns

scholarly journals A Neural Network Prefetcher for Arbitrary Memory Access Patterns

2020 ◽  
Vol 16 (4) ◽  
pp. 1-27 ◽  
Author(s):  
Leeor Peled ◽  
Uri Weiser ◽  
Yoav Etsion
Keyword(s):  
Neural Network ◽  
Memory Access ◽  
Access Patterns

scholarly journals Recovering memory access patterns of executable programs

2014 ◽  
Vol 80 ◽  
pp. 440-456
Author(s):  
Alain Ketterlin ◽  
Philippe Clauss
Keyword(s):  
Memory Access ◽  
Access Patterns ◽  
Executable Programs

Impact of GPU memory access patterns on FDTD

2012 ◽  
Author(s):  
Matthew Livesey ◽  
James F. Stack ◽  
Fumie Costen ◽  
Takeshi Nanri ◽  
Norimasa Nakashima ◽  
...  
Keyword(s):  
Memory Access ◽  
Access Patterns
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