scholarly journals Multi-Level Simulation Platform of Network-on-Chip forDesign Space Exploration

2011 ◽  
pp. 504-509 ◽  
Author(s):  
Kuei-Chung Chang ◽  
Chien-Hao Chen
Keyword(s):  
Space Exploration ◽  
Network On Chip ◽  
Simulation Platform ◽  
Multi Level ◽  
On Chip

scholarly journals Network-on-Chip Irregular Topology Optimization for Real-Time and Non-Real-Time Applications

Micromachines ◽  
2021 ◽  
Vol 12 (10) ◽  
pp. 1196
Author(s):  
Samuel da Silva Oliveira ◽  
Bruno Motta de Carvalho ◽  
Márcio Eduardo Kreutz
Keyword(s):  
Real Time ◽  
Communication Networks ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Network On Chip ◽  
Chip Area ◽  
Average Latency ◽  
Real Time Applications ◽  
On Chip

Network-on-Chip is a good approach to working on intra-chip communication. Networks with irregular topologies may be better suited for specific applications because of their architectural nature. A good design space exploration can help the design of the network to obtain more optimized topologies. This paper proposes a way of optimizing networks with irregular topologies through the use of a genetic algorithm. The network proposed here has heterogeneous routers that aim to optimize the network and support applications with real-time tasks. The goal is to find networks that are optimized for average latency and percentage of real-time packets delivered within the deadline. The results show that we have been able to find networks that can deliver all the real-time packets, obtain acceptable latency values, and shrink the chip area.

scholarly journals Design Space Exploration of 3D Network-on-Chip

2018 ◽  
Vol 14 (3) ◽  
pp. 1-26 ◽  
Author(s):  
Dongjin Lee ◽  
Sourav Das ◽  
Dae Hyun Kim ◽  
Janardhan Rao Doppa ◽  
Partha Pratim Pande
Keyword(s):  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Network On Chip ◽  
3D Network ◽  
On Chip
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