Electroless Ni alloy plating as a diffusion barrier for through silicon vias in three-dimensional packaging

2015 ◽  
Vol 55 (2S) ◽  
pp. 02BC04 ◽  
Author(s):  
Taeyoo Kim ◽  
Byungwook Ahn ◽  
SeungKyu Lim ◽  
Hwajin Son ◽  
Sujeong Suh
Keyword(s):  
Diffusion Barrier ◽  
Three Dimensional ◽  
Through Silicon Vias ◽  
Ni Alloy ◽  
Alloy Plating ◽  
Silicon Vias ◽  
Electroless Ni

Reliable Design of Electroplated Copper Through Silicon Vias

2010 ◽  
Author(s):  
Xi Liu ◽  
Qiao Chen ◽  
Venkatesh Sundaram ◽  
Sriram Muthukumar ◽  
Rao R. Tummala ◽  
...  
Keyword(s):  
System Integration ◽  
Coefficient Of Thermal Expansion ◽  
Three Dimensional ◽  
Interfacial Stress ◽  
Through Silicon Vias ◽  
Fabrication Defects ◽  
Reliable Design ◽  
Electroplated Copper ◽  
Key Enabling Technologies ◽  
Silicon Vias

Through-silicon vias (TSVs), being one of the key enabling technologies for 3D system integration, are being used in various 3D vertically stacked devices. As TSVs are relatively new, there is not enough information in available literature on the thermo-mechanical reliability of TSVs. Due to the high coefficient of thermal expansion (CTE) mismatch between Si and the Cu vias, “Cu pumping” will occur at high temperature and “Cu sinking” will occur at low temperature, which may induce large stress in SiO2, interfacial stress at Cu/SiO2 interface and plastic deformation in Cu core. The thermal-mechanical stress can potentially cause interfacial debonding, cohesive cracking in dielectric layers or Cu core, causing some reliability issues. Thus, in this paper, three-dimensional thermo-mechanical finite-element models have been built to analyze the stress/strain distribution in the TSV structures. A comparative analysis of different via designs, such as circular, square, and annular vias has been performed. In addition, defects due to fabrication such as voids in the Cu core during electroplating and Cu pad undercutting due to over-etching are considered in the models, and it is seen that these fabrication defects are detrimental to TSV reliability.

Formation of Through-Silicon-Vias by Laser Drilling and Deep Reactive Ion Etching

2004 ◽  
Author(s):  
Ronald Hon ◽  
Shawn X. D. Zhang ◽  
S. W. Ricky Lee
Keyword(s):  
Reactive Ion Etching ◽  
Three Dimensional ◽  
Laser Drilling ◽  
Wet Etching ◽  
Ion Etching ◽  
Through Silicon Vias ◽  
Deep Reactive Ion Etching ◽  
Definition Of ◽  
Silicon Vias ◽  
Wafer Thinning

The focus of this study is on the fabrication of through silicon vias (TSV) for three dimensional packaging. According to IPC-6016, the definition of microvias is a hole with a diameter of less than or equal to 150 μm. In order to meet this requirement, laser drilling and deep reactive ion etching (but not wet etching) are used to make the microvias. Comparisons between these two different methods are carried out in terms of wall straightness, smoothness, smallest via produced and time needed for fabrication. In addition, discussion on wafer thinning for making through silicon microvias is given as well.

Characterization of thermal stresses in through-silicon vias for three-dimensional interconnects by bending beam technique

2012 ◽  
Vol 100 (4) ◽  
pp. 041901 ◽  
Author(s):  
Suk-Kyu Ryu ◽  
Tengfei Jiang ◽  
Kuan H. Lu ◽  
Jay Im ◽  
Ho-Young Son ◽  
...  
Keyword(s):  
Thermal Stresses ◽  
Three Dimensional ◽  
Through Silicon Vias ◽  
Silicon Vias ◽  
Beam Technique

A Thermal Isolation Technique Using Through-Silicon Vias for Three-Dimensional ICs

2013 ◽  
Vol 60 (3) ◽  
pp. 1282-1287 ◽  
Author(s):  
Sanming Hu ◽  
Yen Yi Germaine Hoe ◽  
Hongyu Li ◽  
Dan Zhao ◽  
Jinglin Shi ◽  
...  
Keyword(s):  
Three Dimensional ◽  
Thermal Isolation ◽  
Through Silicon Vias ◽  
Isolation Technique ◽  
Silicon Vias
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