Implementation of Complementary Metal–Oxide–Semiconductor Microelectromechanical Systems Lorentz Force Two Axis Angular Actuator

2012 ◽  
Vol 51 (6S) ◽  
pp. 06FL09 ◽  
Author(s):  
Chih-Ming Sun ◽  
Chung-Lin Wu ◽  
Chuanwei Wang ◽  
Chun-I Chang ◽  
Ming-Chuen Yip ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Lorentz Force ◽  
Microelectromechanical Systems ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor

Effects of etching holes on complementary metal oxide semiconductor–microelectromechanical systems capacitive structure

2012 ◽  
Vol 24 (3) ◽  
pp. 310-317 ◽  
Author(s):  
Wei-Hsiang Tu ◽  
Wen-Chang Chu ◽  
Chih-Kung Lee ◽  
Pei-Zen Chang ◽  
Yuh-Chung Hu
Keyword(s):  
Metal Oxide ◽  
Microelectromechanical Systems ◽  
Sacrificial Layer ◽  
Estimation Method ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Fringe Field ◽  
Large Area ◽  
Fringing Field

Etching the large area of sacrificial layer under the microstructure to be released is a common method used in microelectromechanical systems technology. In order to completely release the microstructures, many etching holes are often required on the microstructure to enable the etchant to completely etch the sacrificial layer. However, the etching holes often alter the electromechanical properties of the micro devices, especially capacitive devices, because the fringe fields induced by the etching holes can significantly alter the electrical properties. This article is aimed at evaluating the fringe field capacitance caused by etching holes on microstructures. The authors aim to find a general capacitance compensation formula for the fringe capacitance of etching holes by the use of ANSYS simulation. According to the simulation results, the design of a capacitive structure with small etching holes is recommended to prevent an extreme capacitance decrease. In conclusion, this article provides a fringing field capacitance estimation method that shows the capacitance compensation tendency of the design of etching holes; this method is expected to be applicable to the design in capacitive devices of complementary metal oxide semiconductor–microelectromechanical systems technology.

Computational study of the staircase molecular conductivity of polyoxovanadates adsorbed on Au(111)

2021 ◽  
Vol 50 (16) ◽  
pp. 5540-5551
Author(s):  
Almudena Notario-Estévez ◽  
Xavier López ◽  
Coen de Graaf
Keyword(s):  
Metal Oxide ◽  
Computational Study ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Molecular Conduction ◽  
Conduction Properties ◽  
Molecular Conductivity

This computational study presents the molecular conduction properties of polyoxovanadates V6O19 (Lindqvist-type) and V18O42, as possible successors of the materials currently in use in complementary metal–oxide semiconductor (CMOS) technology.

scholarly journals Universal Filter Based on Compact CMOS Structure of VDDDA

Sensors ◽  
2021 ◽  
Vol 21 (5) ◽  
pp. 1683
Author(s):  
Winai Jaikla ◽  
Fabian Khateb ◽  
Tomasz Kulej ◽  
Koson Pitaksuttayaprot
Keyword(s):  
Metal Oxide ◽  
Dynamic Range ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Experimental Results ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Voltage Gain ◽  
Universal Filter ◽  
Mos Transistor

This paper proposes the simulated and experimental results of a universal filter using the voltage differencing differential difference amplifier (VDDDA). Unlike the previous complementary metal oxide semiconductor (CMOS) structures of VDDDA that is present in the literature, the present one is compact and simple, owing to the employment of the multiple-input metal oxide semiconductor (MOS) transistor technique. The presented filter employs two VDDDAs, one resistor and two grounded capacitors, and it offers low-pass: LP, band-pass: BP, band-reject: BR, high-pass: HP and all-pass: AP responses with a unity passband voltage gain. The proposed universal voltage mode filter has high input impedances and low output impedance. The natural frequency and bandwidth are orthogonally controlled by using separated transconductance without affecting the passband voltage gain. For a BP filter, the root mean square (RMS) of the equivalent output noise is 46 µV, and the third intermodulation distortion (IMD3) is −49.5 dB for an input signal with a peak-to peak of 600 mV, which results in a dynamic range (DR) of 73.2 dB. The filter was designed and simulated in the Cadence environment using a 0.18-µm CMOS process from Taiwan semiconductor manufacturing company (TSMC). In addition, the experimental results were obtained by using the available commercial components LM13700 and AD830. The simulation results are in agreement with the experimental one that confirmed the advantages of the filter.

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