scholarly journals Effects of low-temperature annealing phosphorous gettering process on the electrical properties of multi-crystalline silicon with a low minority carrier lifetime

2013 ◽  
Vol 62 (11) ◽  
pp. 110101
Author(s):  
Jiang Li-Li ◽  
Lu Zhong-Lin ◽  
Zhang Feng-Ming ◽  
Lu Xiong
Keyword(s):  
Electrical Properties ◽  
Low Temperature ◽  
Carrier Lifetime ◽  
Minority Carrier ◽  
Crystalline Silicon ◽  
Minority Carrier Lifetime ◽  
Low Temperature Annealing

The Effects of Impurity Codoping on the Electrical Properties of Erbium Ions in Crystalline Silicon

1996 ◽  
Vol 422 ◽  
Author(s):  
S. Libertino ◽  
S. Coffa ◽  
R. Mosca ◽  
E. Gombia
Keyword(s):  
Electrical Properties ◽  
Band Gap ◽  
Carrier Lifetime ◽  
Minority Carrier ◽  
Crystalline Silicon ◽  
Deep Level ◽  
Minority Carrier Lifetime ◽  
Erbium Ions ◽  
Donor Behaviour ◽  
Energetic Position

AbstractWe have investigated the effects of oxygen codoping and thermal annealing on the deep level spectrum and carrier lifetime of Er implanted crystalline Si. It is found that oxygen codoping produces a dramatic modification in the concentration and energetic position of Er-related deep levels in the Si band gap. In particular the formation of Er-O complexes is shown to produce a promotion from deep to shallow levels. This effect is the major responsible of the enhancement of Er donor behaviour in presence of oxygen and also produces a large increase in the minority carrier lifetime

The Effect of Hydrogenation on the Electrical Properties of Crystalline Silicon

1992 ◽  
Vol 262 ◽  
Author(s):  
Jacques I. Pankove
Keyword(s):  
Electrical Properties ◽  
Carrier Lifetime ◽  
Minority Carrier ◽  
Crystalline Silicon ◽  
Surface Recombination ◽  
Minority Carrier Lifetime ◽  
Lower Surface ◽  
Dangling Bonds ◽  
Defect Passivation ◽  
Different Temperatures

ABSTRACTHydrogen ties Si dangling bonds at defects as well as near impurities. Defect passivation leads to dramatically lower surface recombination and increased minority carrier lifetime. Dopant neutralization increases the resistivity of the crystal and the mobility of carriers. The neutralization of donors and acceptors is optimum at different temperatures. Deep levels can also be neutralized.

Carrier Lifetime Measurements by Photoconductance at Low Temperature on Passivated Crystalline Silicon Wafers

2013 ◽  
Vol 1536 ◽  
pp. 119-125 ◽  
Author(s):  
Guillaume Courtois ◽  
Bastien Bruneau ◽  
Igor P. Sobkowicz ◽  
Antoine Salomon ◽  
Pere Roca i Cabarrocas
Keyword(s):  
Low Temperature ◽  
Electron Mobility ◽  
Carrier Density ◽  
Carrier Lifetime ◽  
Minority Carrier ◽  
Crystalline Silicon ◽  
Silicon Wafers ◽  
Doping Density ◽  
Lifetime Measurements ◽  
Effective Lifetime

ABSTRACTWe propose an implementation of the PCD technique to minority carrier effective lifetime assessment in crystalline silicon at 77K. We focus here on (n)-type, FZ, polished wafers passivated by a-Si:H deposited by PECVD at 200°C. The samples were immersed into liquid N2 contained in a beaker placed on a Sinton lifetime tester. Prior to be converted into lifetimes, data were corrected for the height shift induced by the beaker. One issue lied in obtaining the sum of carrier mobilities at 77K. From dark conductance measurements performed on the lifetime tester, we extracted an electron mobility of 1.1x104 cm².V-1.s-1 at 77K, the doping density being independently calculated in order to account for the freezing effect of dopants. This way, we could obtain lifetime curves with respect to the carrier density. Effective lifetimes obtained at 77K proved to be significantly lower than at RT and not to depend upon the doping of the a-Si:H layers. We were also able to experimentally verify the expected rise in the implied Voc, which, on symmetrically passivated wafers, went up from 0.72V at RT to 1.04V at 77K under 1 sun equivalent illumination.

Minority carrier lifetime scan map in crystalline silicon wafers

1999 ◽  
Vol 70 (10) ◽  
pp. 4044-4046 ◽  
Author(s):  
J. Gervais ◽  
O. Palais ◽  
L. Clerc ◽  
S. Martinuzzi
Keyword(s):  
Carrier Lifetime ◽  
Minority Carrier ◽  
Crystalline Silicon ◽  
Minority Carrier Lifetime ◽  
Silicon Wafers

Effects of Impurities Distribution on the Crystal Structure and Electrical Properties of Multi-Crystalline Silicon Ingots

2011 ◽  
Vol 675-677 ◽  
pp. 101-104
Author(s):  
Qi Zhi Xing ◽  
Wei Dong ◽  
Shu Ang Shi ◽  
Guo Bin Li ◽  
Yi Tan
Keyword(s):  
Electrical Properties ◽  
Minority Carrier ◽  
Crystalline Silicon ◽  
Melting Furnace ◽  
Minority Carrier Lifetime ◽  
Vacuum Induction Melting ◽  
Induction Melting ◽  
Columnar Crystal ◽  
P Type ◽  
Crystal Region

Multi-crystalline silicon ingots were prepared by directional solidification using vacuum induction melting furnace. The content of aluminum and iron deeply decreased in the columnar crystal region of the multi-crystalline silicon ingots. The columnar crystal growth broke off corresponded to the iron contents sharply increased. The height of columnar crystal in the silicon ingots related to the pulling rates had been clarified by the constitutional supercooling theory. The maximum of the resistivity and the minority carrier lifetime closed to the transition zone where the conductive type changed from p-type to n-type in silicon ingots. Further analysis suggested that the electrical properties were related to the contents of shallow level impurities aluminum, boron and phosphorus.

Minority Carrier Lifetime Improvement of Multicrystalline Silicon Using Combined Saw Damage Gettering and Emitter Formation

2015 ◽  
Vol 242 ◽  
pp. 126-132 ◽  
Author(s):  
George Martins ◽  
Ruy S. Bonilla ◽  
Toby Burton ◽  
P. MacDonald ◽  
Peter R. Wilshaw
Keyword(s):  
Carrier Lifetime ◽  
Minority Carrier ◽  
Crystalline Silicon ◽  
Minority Carrier Lifetime ◽  
High Concentration ◽  
Production Methods ◽  
Cell Efficiency ◽  
Annealing Conditions ◽  
Maximum Lifetime ◽  
Current Production

In this work we use Saw Damage Gettering (SDG) in combination with emitter formation to improve the minority carrier lifetime of highly contaminated multi-crystalline silicon wafers. This process is applied to wafers from the bottom of ingots, commonly referred to as the “red zone”, which are currently discarded since their high concentration of impurities limits the efficiency of solar cells produced therefrom. SDG is a potentially simple technique designed to upgrade these wafers. In this technique, bulk impurities are dissolved via annealing. The wafers are then cooled which generates a super-saturation of impurities in solution. The system then relaxes through the formation of precipitates in the saw damaged region. SDG is shown to be enhanced when using a temperature dependent cooling rate which maximizes the flux of impurities to the saw damaged regions. In addition, these benefits were observed even after an additional gettering process occurring during an emitter formation procedure. The SDG annealing conditions required to achieve the maximum lifetime were altered by the introduction of the emitter formation process. The enhancement generated by the SDG process may be sufficient to enable red-zone wafers to be processed is the same manner as higher quality no-red zone wafer wafers without adversely affecting the resultant cell efficiency. Due to its simplicity, it is expected that SDG can easily be incorporated into current production methods.

Minority Carrier Lifetime Behavior in Crystalline Silicon in Rapid Laser Heating

2012 ◽  
Vol 51 ◽  
pp. 03CA04
Author(s):  
Toshiyuki Sameshima ◽  
Koichi Betsuin ◽  
Tomohisa Mizuno ◽  
Naoki Sano
Keyword(s):  
Laser Heating ◽  
Carrier Lifetime ◽  
Minority Carrier ◽  
Crystalline Silicon ◽  
Minority Carrier Lifetime
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