Minimal forbidden subgraphs of reducible graph properties

2001 ◽  
Vol 21 (1) ◽  
pp. 111 ◽  
Author(s):  
Amelie Berger
Keyword(s):  
Forbidden Subgraphs ◽  
Graph Properties ◽  
Reducible Graph

scholarly journals Some results on decomposable and reducible graph properties

2012 ◽  
Vol 312 (16) ◽  
pp. 2491-2497
Author(s):  
Michael J. Dorfling
Keyword(s):  
Graph Properties ◽  
Reducible Graph

scholarly journals Toughness, Forbidden Subgraphs and Pancyclicity

2021 ◽  
Vol 37 (3) ◽  
pp. 839-866
Author(s):  
Wei Zheng ◽  
Hajo Broersma ◽  
Ligong Wang
Keyword(s):  
Recent Article ◽  
Forbidden Subgraph ◽  
Forbidden Subgraphs ◽  
Free Graph ◽  
Induced Subgraph ◽  
Complete Answer ◽  
Open Case

AbstractMotivated by several conjectures due to Nikoghosyan, in a recent article due to Li et al., the aim was to characterize all possible graphs H such that every 1-tough H-free graph is hamiltonian. The almost complete answer was given there by the conclusion that every proper induced subgraph H of $$K_1\cup P_4$$ K 1 ∪ P 4 can act as a forbidden subgraph to ensure that every 1-tough H-free graph is hamiltonian, and that there is no other forbidden subgraph with this property, except possibly for the graph $$K_1\cup P_4$$ K 1 ∪ P 4 itself. The hamiltonicity of 1-tough $$K_1\cup P_4$$ K 1 ∪ P 4 -free graphs, as conjectured by Nikoghosyan, was left there as an open case. In this paper, we consider the stronger property of pancyclicity under the same condition. We find that the results are completely analogous to the hamiltonian case: every graph H such that any 1-tough H-free graph is hamiltonian also ensures that every 1-tough H-free graph is pancyclic, except for a few specific classes of graphs. Moreover, there is no other forbidden subgraph having this property. With respect to the open case for hamiltonicity of 1-tough $$K_1\cup P_4$$ K 1 ∪ P 4 -free graphs we give infinite families of graphs that are not pancyclic.

scholarly journals Forbidden subgraphs of graphs uniquely Hamiltonian-connected from a vertex

1998 ◽  
Vol 187 (1-3) ◽  
pp. 281-290 ◽  
Author(s):  
George R.T. Hendry ◽  
C.J. Knickerbocker ◽  
Patti Frazer Lock ◽  
Michael Sheard
Keyword(s):  
Forbidden Subgraphs ◽  
Hamiltonian Connected

scholarly journals A Quasi-Hole Detection Algorithm for Recognizing k-Distance-Hereditary Graphs, with k < 2

Algorithms ◽  
2021 ◽  
Vol 14 (4) ◽  
pp. 105
Author(s):  
Serafino Cicerone
Keyword(s):  
Polynomial Time ◽  
Detection Algorithm ◽  
Recognition Algorithm ◽  
Forbidden Subgraphs ◽  
Induced Subgraph ◽  
Hole Detection

Cicerone and Di Stefano defined and studied the class of k-distance-hereditary graphs, i.e., graphs where the distance in each connected induced subgraph is at most k times the distance in the whole graph. The defined graphs represent a generalization of the well known distance-hereditary graphs, which actually correspond to 1-distance-hereditary graphs. In this paper we make a step forward in the study of these new graphs by providing characterizations for the class of all the k-distance-hereditary graphs such that k<2. The new characterizations are given in terms of both forbidden subgraphs and cycle-chord properties. Such results also lead to devise a polynomial-time recognition algorithm for this kind of graph that, according to the provided characterizations, simply detects the presence of quasi-holes in any given graph.

You Only Traverse Twice: A YOTT Placement, Routing, and Timing Approach for CGRAs

2021 ◽  
Vol 20 (5s) ◽  
pp. 1-25
Author(s):  
Michael Canesche ◽  
Westerley Carvalho ◽  
Lucas Reis ◽  
Matheus Oliveira ◽  
Salles Magalhães ◽  
...  
Keyword(s):  
Execution Time ◽  
High Performance ◽  
Coarse Grained ◽  
Optimal Placement ◽  
Greedy Heuristics ◽  
High Quality ◽  
Solution Quality ◽  
Graph Traversal ◽  
Trade Offs ◽  
Graph Properties

Coarse-grained reconfigurable architecture (CGRA) mapping involves three main steps: placement, routing, and timing. The mapping is an NP-complete problem, and a common strategy is to decouple this process into its independent steps. This work focuses on the placement step, and its aim is to propose a technique that is both reasonably fast and leads to high-performance solutions. Furthermore, a near-optimal placement simplifies the following routing and timing steps. Exact solutions cannot find placements in a reasonable execution time as input designs increase in size. Heuristic solutions include meta-heuristics, such as Simulated Annealing (SA) and fast and straightforward greedy heuristics based on graph traversal. However, as these approaches are probabilistic and have a large design space, it is not easy to provide both run-time efficiency and good solution quality. We propose a graph traversal heuristic that provides the best of both: high-quality placements similar to SA and the execution time of graph traversal approaches. Our placement introduces novel ideas based on “you only traverse twice” (YOTT) approach that performs a two-step graph traversal. The first traversal generates annotated data to guide the second step, which greedily performs the placement, node per node, aided by the annotated data and target architecture constraints. We introduce three new concepts to implement this technique: I/O and reconvergence annotation, degree matching, and look-ahead placement. Our analysis of this approach explores the placement execution time/quality trade-offs. We point out insights on how to analyze graph properties during dataflow mapping. Our results show that YOTT is 60.6 , 9.7 , and 2.3 faster than a high-quality SA, bounding box SA VPR, and multi-single traversal placements, respectively. Furthermore, YOTT reduces the average wire length and the maximal FIFO size (additional timing requirement on CGRAs) to avoid delay mismatches in fully pipelined architectures.

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