3D-Stacked Memory For Shared-Memory Multithreaded Workloads

ECMS 2020 Proceedings edited by Mike Steglich, Christian Mueller, Gaby Neumann, Mathias Walther ◽

10.7148/2020-0368 ◽

2020 ◽

Author(s):

Sourav Bhattacharya ◽

Horacio Gonzalez-Velez

Keyword(s):

Shared Memory ◽

Multithreaded Workloads ◽

Stacked Memory

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A Workload-Adaptive and Reconfigurable Bus Architecture for Multicore Processors

International Journal of Reconfigurable Computing ◽

10.1155/2010/205852 ◽

2010 ◽

Vol 2010 ◽

pp. 1-22 ◽

Cited By ~ 5

Author(s):

Shoaib Akram ◽

Alexandros Papakonstantinou ◽

Rakesh Kumar ◽

Deming Chen

Keyword(s):

Shared Memory ◽

Interconnection Networks ◽

Interconnection Network ◽

Multicore Processors ◽

Scale Up ◽

Cost Effective ◽

Reconfigurable Logic ◽

Multithreaded Workloads ◽

Adaptive Policies ◽

Bus Architecture

Interconnection networks for multicore processors are traditionally designed to serve a diversity of workloads. However, different workloads or even different execution phases of the same workload may benefit from different interconnect configurations. In this paper, we first motivate the need for workload-adaptive interconnection networks. Subsequently, we describe an interconnection network framework based on reconfigurable switches for use in medium-scale (up to 32 cores) shared memory multicore processors. Our cost-effective reconfigurable interconnection network is implemented on a traditional shared bus interconnect with snoopy-based coherence, and it enables improved multicore performance. The proposed interconnect architecture distributes the cores of the processor into clusters with reconfigurable logic between clusters to support workload-adaptive policies for inter-cluster communication. Our interconnection scheme is complemented by interconnect-aware scheduling and additional interconnect optimizations which help boost the performance of multiprogramming and multithreaded workloads. We provide experimental results that show that the overall throughput of multiprogramming workloads (consisting of two and four programs) can be improved by up to 60% with our configurable bus architecture. Similar gains can be achieved also for multithreaded applications as shown by further experiments. Finally, we present the performance sensitivity of the proposed interconnect architecture on shared memory bandwidth availability.

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