scholarly journals Ultra-Low-Voltage IC Design Methods

2020 ◽  
Author(s):  
Daniel Arbet ◽  
Lukas Nagy ◽  
Viera Stopjakova
Keyword(s):  
Low Voltage ◽  
Design Methods ◽  
Ic Design

A comparison of mixed gate array and custom IC design methods

1984 ◽  
Author(s):  
C. Erdelyi ◽  
R. Bechade ◽  
M. Concannon ◽  
W. Hoffman
Keyword(s):  
Design Methods ◽  
Ic Design ◽  
Gate Array

scholarly journals Special Aspects of Submicrometer MOSFETs Simulation for Low Voltage, Ultra-low Power CMOS IC Design

2018 ◽  
pp. 412-414
Author(s):  
Lebedev Sergey V. ◽  
Petrosyants Konstantin O. ◽  
Stakhin Veniamin G. ◽  
Kharitonov Igor A.
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Ic Design ◽  
Ultra Low Power ◽  
Low Power Cmos ◽  
Cmos Ic

MOS transistor modeling for low-voltage and low-power analog IC design

1997 ◽  
Vol 39 (1-4) ◽  
pp. 59-76 ◽  
Author(s):  
Christian C. Enz ◽  
Eric A. Vittoz
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Ic Design ◽  
Mos Transistor ◽  
Analog Ic

Low-voltage analog IC design in CMOS technology

1995 ◽  
Vol 42 (11) ◽  
pp. 955-958 ◽  
Author(s):  
A.L. Coban ◽  
P.E. Allen ◽  
Xudong Shi
Keyword(s):  
Low Voltage ◽  
Cmos Technology ◽  
Ic Design ◽  
Analog Ic

Low Voltage Low Power Fully Integrated Chaos Generator

2018 ◽  
Vol 27 (10) ◽  
pp. 1850155 ◽  
Author(s):  
Jie Jin ◽  
LV Zhao
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Supply Voltage ◽  
Electronic Components ◽  
Ic Design ◽  
Chip Area ◽  
Fully Integrated ◽  
Chaos Generator ◽  
Wide Range

A low voltage low power fully integrated chaos generator is presented in this paper. Comparing with the conventional off-the-shelf electronic components-based chaos generators, the designed circuit is fully integrated, and it achieves lower supply voltage, lower power dissipation and smaller chip area. The proposed fully integrated chaos generator is verified with GlobalFoundries 0.18[Formula: see text][Formula: see text]m CMOS 1P6M RF process using Cadence IC Design Tools. The simulation results demonstrate that the fully integrated chaos generator consumes only 17[Formula: see text]mW from [Formula: see text]2.5[Formula: see text]V supply voltage. Moreover, the chip area of the chaos generator is only 1.755[Formula: see text]mm2 including the testing pads, and it has a wide range of practical application prospects.

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