scholarly journals High-Speed Area-Efficient Implementation of AES Algorithm on Reconfigurable Platform

2020 ◽  
Author(s):  
Altaf O. Mulani ◽  
Pradeep B. Mane
Keyword(s):  
High Speed ◽  
Efficient Implementation ◽  
Aes Algorithm ◽  
Reconfigurable Platform ◽  
Area Efficient

scholarly journals High Speed Area Efficient FPGA Implementation of AES Algorithm

2018 ◽  
Vol 7 (3) ◽  
pp. 151
Author(s):  
P. B. Mane ◽  
A. O. Mulani
Keyword(s):  
Power Consumption ◽  
High Throughput ◽  
High Speed ◽  
Advanced Encryption Standard ◽  
Digital Information ◽  
Unauthorized Access ◽  
Aes Algorithm ◽  
Symmetric Key ◽  
Reconfigurable Platform ◽  
Symmetric Key Cryptography

Now a day digital information is very easy to process, but it allows unauthorized users to access this information. To protect this information from unauthorized access, Advanced Encryption Standard (AES) is one of the most frequently used symmetric key cryptography algorithm. Main objective of this paper is to implement fast and secure AES algorithm on reconfigurable platform. In this paper, AES algorithm is designed with the aim to achieve less power consumption and high throughput. Keys are generated using MATLAB and remaining algorithm is designed using Xilinx SysGen, implemented on Nexys4 and simulated using Simulink. Synthesis result shows that it consumes 121 slice registers and its operating frequency is 1102.536 MHz. Throughput of the overall system is 14.1125 Gbps.

scholarly journals High Speed Area Efficient FPGA Implementation of AES Algorithm

2018 ◽  
Vol 7 (3) ◽  
pp. 157
Author(s):  
P. B. Mane ◽  
A. O. Mulani
Keyword(s):  
Power Consumption ◽  
High Throughput ◽  
High Speed ◽  
Advanced Encryption Standard ◽  
Digital Information ◽  
Unauthorized Access ◽  
Aes Algorithm ◽  
Symmetric Key ◽  
Reconfigurable Platform ◽  
Symmetric Key Cryptography

Now a day digital information is very easy to process, but it allows unauthorized users to access this information. To protect this information from unauthorized access, Advanced Encryption Standard (AES) is one of the most frequently used symmetric key cryptography algorithm. Main objective of this paper is to implement fast and secure AES algorithm on reconfigurable platform. In this paper, AES algorithm is designed with the aim to achieve less power consumption and high throughput. Keys are generated using MATLAB and remaining algorithm is designed using Xilinx SysGen, implemented on Nexys4 and simulated using Simulink. Synthesis result shows that it consumes 121 slice registers and its operating frequency is 1102.536 MHz. Throughput of the overall system is 14.1125 Gbps.

scholarly journals Area Efficient Implementation of MTI Processing Module on a Reconfigurable Platform

2014 ◽  
Vol 2014 ◽  
pp. 1-7 ◽  
Author(s):  
Munaza Yousuf ◽  
Arshad Aziz ◽  
Riaz Mahmud
Keyword(s):  
High Speed ◽  
Low Cost ◽  
Digital Design ◽  
Radar Signal ◽  
Field Programmable ◽  
Processing Module ◽  
Reconfigurable Platform ◽  
High Level ◽  
High Processing ◽  
Area Efficient

This paper presents an area efficient Field Programmable Gate Array (FPGA) based digital design of a processing module for MTI radar. Signal contaminated with noise and clutter is modelled to test the efficacy of the design algorithms. For flexibility of design and to achieve optimized results, we have combined the high-level utility of MATLAB with the flexibility and optimization on FPGA for this implementation. Two- and three-pulse cancellers are chosen for design due to its simplicity in both concept and implementation. The results obtained are efficient in terms of enhanced throughput per Slice (TPA) of 1.146, that is, occupying fewer area resources on hardware while achieving optimized speed. The outcomes show that this design of MTI radar processor has many advantages, such as high processing precision, strong processing ability, real time, and low cost. All these advantages greatly contribute to the design requirements and make it appropriate for the application of high-speed signal processing.

scholarly journals A Low Power, Area Efficient Implementation of AES Algorithm

2019 ◽  
Vol 8 (9S3) ◽  
pp. 1385-1392
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Cmos Technology ◽  
Fpga Implementation ◽  
Efficient Implementation ◽  
Aes Algorithm ◽  
Area Efficient

Encryption is a procedure of convert readable information into encoded appearance so that it can’t be interpreted by the intruder. Paper presents the FPGA implementation of a low power, neighborhood efficient AES algorithm for encrypting data. From the results it has been experimental that the enhanced technique has reduced the power consumption and area compared to the existing methods. The implementation is done in 90 nm and 65 nm CMOS technology using Quartus for Cyclone II and Cyclone III

Design of area-efficient high speed 4 × 4 Wallace tree multiplier using quantum-dot cellular automata

2020 ◽  
Author(s):  
A. Arunkumar Gudivada ◽  
K. Jayaram Kumar ◽  
Srinivasa Rao Jajula ◽  
Durga Prasad Siddani ◽  
Praveen Kumar Poola ◽  
...  
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
High Speed ◽  
Quantum Dot Cellular Automata ◽  
Wallace Tree ◽  
Wallace Tree Multiplier ◽  
Area Efficient
Sign in / Sign up

Export Citation Format

Share Document