scholarly journals IntelliSoC: A System Level Design and Conception of a System- on-a-Chip (SoC) to Cognitive Agents Architecture

2019 ◽  
Author(s):  
Diego Ferreira ◽  
Augusto Loureiro da Costa ◽  
Wagner Luiz Alves De Oliveira
Keyword(s):  
System Level ◽  
System Level Design ◽  
Cognitive Agents ◽  
System On A Chip ◽  
Level Design

scholarly journals System Level Design and Conception of a System-on-a-Chip (SoC) for Cognitive Robotics

2021 ◽  
Author(s):  
Diego Stéfano Fonseca Ferreira ◽  
Augusto Loureiro da Costa ◽  
Wagner Luiz Alves De Oliveira ◽  
Alejandro Rafael Garcia Ramirez
Keyword(s):  
Cognitive Model ◽  
Cognitive Robotics ◽  
System Level ◽  
System Level Design ◽  
Cognitive Level ◽  
Knowledge Based System ◽  
Knowledge Based ◽  
System On A Chip ◽  
Level Design ◽  
Complex Knowledge

In this work, a system level design and conception of a System-on-a-Chip (SoC) for the execution of cognitive agents in robotics will be presented. The cognitive model of the Concurrent Autonomous Agent (CAA), which was already successfully applied in several robotics applications, is used as a reference for the development of the hardware architecture. This cognitive model comprises three levels that run concurrently, namely the reactive level (perception-action cycle that executes predefined behaviours), the instinctive level (receives goals from cognitive level and uses a knowledge based system for selecting behaviours in the reactive level) and the cognitive level (planning). For the development of such system level hardware model, the C++ library SystemC with Transaction Level Modelling (TLM) 2.0 will be used. A system model of a module that executes a knowledge based system is presented, followed by a system level description of a processor dedicated to the execution of the Graphplan planning algorithm. The buses interconnecting these modules are modelled by the TLM generic payload. Results from simulated experiments with complex knowledge bases for solving planning problems in different robotics contexts demonstrate the correctness of the proposed architecture. Finally, a discussion on performance gains takes place in the end.

Low-complexity SPICE Analog Behavioral Modeling of the ideal battery for system level design

2020 ◽  
Author(s):  
Ariel Jimenez ◽  
Natalia Morales ◽  
Carlos Paez ◽  
Arturo Fajardo ◽  
Gabriel Perilla
Keyword(s):  
Low Complexity ◽  
Behavioral Modeling ◽  
System Level ◽  
System Level Design ◽  
Level Design ◽  
The Ideal

A Case Study of FPGA Blokus Duo Solver by System-Level Design

2014 ◽  
Vol 42 (4) ◽  
pp. 57-62
Author(s):  
Yuki Ando ◽  
Masataka Ogawa ◽  
Yuya Mizoguchi ◽  
Kouta Kumagai ◽  
Miaw Torng-Der ◽  
...  
Keyword(s):  
System Level ◽  
System Level Design ◽  
Level Design

All together now [system-level design]

2005 ◽  
Vol 3 (4) ◽  
pp. 34-39
Author(s):  
M. Lippett ◽  
A. Oung
Keyword(s):  
System Level ◽  
System Level Design ◽  
Level Design
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