scholarly journals Fast Fourier Transform Processors: Implementing FFT and IFFT Cores for OFDM Communication Systems

10.5772/36176 ◽  
2012 ◽  
Author(s):  
A. Cortes ◽  
I. Velez ◽  
M. Turrillas ◽  
J. F.
Keyword(s):  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Communication Systems

scholarly journals Channel estimation of OFDM in C-band communication systems under different distribution conditions

2021 ◽  
Vol 23 (3) ◽  
pp. 1778
Author(s):  
Heba Abdul-Jaleel Al-Asady ◽  
Hassan Falah Fakhruldeen ◽  
Mustafa Qahtan Alsudani
Keyword(s):  
Fourier Transform ◽  
Channel Estimation ◽  
Fast Fourier Transform ◽  
Communication Systems ◽  
Orthogonal Frequency Division Multiplexing ◽  
Frequency Division Multiplexing ◽  
Frequency Division ◽  
Ofdm System ◽  
High Data ◽  
High Efficient

<p>Orthogonal frequency division multiplexing (OFDM) is a transmission system that uses multiple orthogonal carriers that are sent out at the same time. OFDM is a technique for mobile and wireless communication that has high-efficient frequency utilization, high data-rate transmission, simple and efficient implementation using the fast Fourier transform (FFT) and the inverse fast Fourier transform (IFFT), and reduces inter symbol interference (ISI) by inserting cyclic prefix (CP). One of the most important approaches in an OFDM system is channel estimation. In this paper, the orthogonal frequency division multiplexing system with the Rayleigh channel module is analyzed for different areas. The proposed approach used large numbers of subcarriers to transmit the signals over 64-QAM modulation with pilot add channel estimation. The accuracy of the OFDM system is shown in the measuring of the relationships of peak power to the noise ratio and bit error rate.</p>

scholarly journals Design of High Speed FFT using Urdhva-Tiryagbhyam Algorithm and Karatsuba Algorithm

2020 ◽  
Vol 9 (4) ◽  
pp. 1904-1908
Keyword(s):  
Image Processing ◽  
Signal Processing ◽  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Execution Time ◽  
Communication Systems ◽  
High Speed ◽  
Floating Point ◽  
Calculation Algorithms ◽  
Floating Point Number

In gift scenario each method has to be compelled to be quick, adept and simple. Fast Fourier transform (FFT) may be a competent algorithmic program to calculate the N purpose Discrete Fourier transform (DFT).It has huge applications in communication systems, signal processing and image processing and instrumentation. However the accomplishment of FFT needs immense range of complicated multiplications, therefore to create this method quick and simple. It’s necessary for a number to be quick and power adept. To influence this problem the mixture of Urdhva Tiryagbhyam associate degreed Karatsuba algorithmic program offers is an adept technique of multiplication [1]. Vedic arithmetic is that the aboriginal system of arithmetic that includes a distinctive technique of calculation supported sixteen Sutras. Using these techniques within the calculation algorithms of the coprocessor can reduce the complexness, execution time, area, power etc. The distinctiveness during this project is Fast Fourier Transform (FFT) style methodology exploitation mixture of Urdhva Tiryagbhyam and Karatsuba algorithmic program based mostly floating point number. By combining these two approaches projected style methodology is time-area-power adept [1] [2]. The code writing is completed in verilog and also the FPGA synthesis on virtex 5 is completed using Xilinx ISE 14.5.

ROM REDUCTION FOR OFDM SYSTEM USING TIME-STEALING STRATEGY

2006 ◽  
Vol 15 (06) ◽  
pp. 907-921
Author(s):  
CHUN-CHING WANG ◽  
YIH-CHUAN LIN ◽  
CHI-YIN LIN
Keyword(s):  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Communication Systems ◽  
High Performance ◽  
Digital Audio ◽  
Fft Processor ◽  
Robust Transmission ◽  
Video Broadcast ◽  
Audio Video ◽  
Combinational Logic Circuit

Modern communication systems frequently exploit the OFDM (Orthogonal Frequency Division Multiplex) technique to obtain a highly robust transmission of multimedia information, such as digital audio/video broadcast. OFDM and most of the other multimedia compression techniques usually require expensive computations, e.g., FFT (Fast Fourier Transform) and IMDCT (Inverse Modified Discrete Cosine Transform) processing. Traditionally, designing FFT and IMDCT separately involves a significant amount of redundancy in hardware. To reduce the required hardware, this investigation proposes a new ROM-sharing design for storing both FFT twiddle factors and IMDCT coefficients in a DAB (Digital Audio Broadcasting) receiver. We first analyze the correlation between FFT operations and IMDCT operations, and then the combinational logic circuit in the FFT processor is modified such that both IMDCT coefficients and FFT twiddle factors can be obtained simultaneously from a shared ROM. This design can also be applied for computing IFFT (Inverse Fast Fourier Transform) and MDCT for DAB transmitter. Compared with the traditional design using separate module scheme, our design does not need extra ROM for IMDCT/MDCT modules. Therefore, the new scheme offers superior solution for combining high-performance FFT (IFFT) operation and IMDCT (MDCT) operation.

scholarly journals Physical IC Design Layout of Memory-Based Real Fast Fourier Transform Architecture using 90nm Technology

2020 ◽  
Vol 8 (5) ◽  
pp. 3681-3685
Keyword(s):  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Communication Systems ◽  
High Speed ◽  
Large Scale ◽  
Low Complexity ◽  
Design Flow ◽  
Digital Subscriber Line ◽  
Ic Design ◽  
Subscriber Line

In this paper we present a low complexity physical IC layout for memory based Real Fast Fourier Transform (RFFT) architecture using 90nm technology. FFT architectures are the most important algorithms in the modern communication systems like and very high bit rate digital subscriber line (VDSL) asymmetric digital subscriber line (ADSL). In this FFT algorithm is based on radix-2 decimation-in-frequency. In order to meet the real time requirements of very large scale integration (VLSI), we designed a low complexity and high speed FFT architecture. The RFFT architecture was realised using Verilog hardware description language (HDL). This architecture is simulated using Native code launch of cadence and synthesized using RTL code complier of cadence tool. Each step of application specific integrated circuit (ASIC) physical IC design flow was synthesized using cadence Innovus 90nm technology and we optimize the design to reduce the area, power and timing requirements

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