scholarly journals Library-Based Gate-Level Current Waveform Modeling for Dynamic Supply Noise Analysis

VLSI Design ◽  
10.5772/34122 ◽  
2012 ◽  
Author(s):  
Mu-Shun Matt ◽  
Chien-Nan Jimmy
Keyword(s):  
Noise Analysis ◽  
Current Waveform ◽  
Waveform Modeling ◽  
Supply Noise

Power Estimation and Power Noise Analysis for CMOS Circuits

1997 ◽  
Vol 07 (01) ◽  
pp. 17-30 ◽  
Author(s):  
An-Chang Deng
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Noise Analysis ◽  
Power Estimation ◽  
Primary Concern ◽  
Cmos Circuits ◽  
Input Stimulus ◽  
Circuit Performance ◽  
Supply Noise ◽  
Power Noise

Power consumption is a primary concern for today's IC designers. However, determining an IC's power consumption is a difficult task, as consumption varies according to input stimulus conditions. This paper will focus on (1) the principal phenomena involved in the power consumption of CMOS circuits, (2) a brief survey of power estimation techniques, and (3) the effect of power-supply noise on circuit performance plus possible solutions to this problem.

Adaptive circuit block model for power supply noise analysis of low power system-on-chip

2009 ◽  
Author(s):  
Matthias Eireiner ◽  
Doris Schmitt-Landsiedel ◽  
Paul Wallner ◽  
Andreas Schone ◽  
Stephan Henzler ◽  
...  
Keyword(s):  
Power System ◽  
Low Power ◽  
Power Supply ◽  
Noise Analysis ◽  
System On Chip ◽  
Block Model ◽  
Supply Noise ◽  
Low Power System ◽  
Adaptive Circuit ◽  
On Chip

Power Supply Noise Analysis Using Neural Network and Genetic Algorithm Based on Automatic Test Equipment

2003 ◽  
Author(s):  
Eric Liau ◽  
Doris Schmitt-Landsiedel
Keyword(s):  
Genetic Algorithm ◽  
Power Supply ◽  
Noise Analysis ◽  
Test Equipment ◽  
Power Supply Noise ◽  
Automatic Test Equipment ◽  
Automatic Test ◽  
Worst Case ◽  
Novel Approach ◽  
Supply Noise

Abstract Power supply noise (PSN) is becoming more severe as technology scales, and can cause signal distortion and increase gate delay. This can further result in improper circuit operation. In this paper, we propose a novel approach based on ATE (automatic test equipment) that teaches neural networks (NN) to correctly classify a set of worst case input patterns with respect to the maximum instantaneous current. This can be thought of as a learning behavior of chip power consumption change due to different input patterns. Then a genetic algorithm (GA) was applied to further optimize this set of NN worst case patterns. A final set of worst case patterns were expected to detect a small critical sequence of high switching currents that was directly related to the worst case power supply noise. This novel diagnosis approach can efficiently identify the defective design or weakness due to PSN as well as locate the defect or weaknesses within the design.

Picosecond Imaging Circuit Analysis of Leakage Currents in CMOS Circuits

2002 ◽  
Author(s):  
Stas Polonsky ◽  
Alan Weger ◽  
Moyra McManus
Keyword(s):  
Power Supply ◽  
Light Emission ◽  
Noise Analysis ◽  
Cmos Circuits ◽  
Photon Detectors ◽  
Leakage Currents ◽  
New Techniques ◽  
Supply Noise ◽  
State Detection ◽  
Logic State

Abstract The light emission from ever increasing OFF-state leakage currents in advanced CMOS technologies can now be reliably measured using existing photon detectors. The measurements of such an emission provide valuable information about the operation of ICs. In this paper we suggest and experimentally confirm two new techniques based on such measurements - Transient Logic State Detection and Power Supply Noise Analysis.

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