Exploiting run-time reconfigurable hardware in the development of automatic fingerprint-based personal recognition applications

Recent Application in Biometrics ◽

10.5772/21500 ◽

2011 ◽

Author(s):

Francisco Fons ◽

Mariano Fons

Keyword(s):

Reconfigurable Hardware ◽

Personal Recognition ◽

Run Time

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Run-Time Reconfigurable Hardware-Software Architecture for PID Motor Control IP Cores

IECON 2006 - 32nd Annual Conference on IEEE Industrial Electronics ◽

10.1109/iecon.2006.347526 ◽

2006 ◽

Cited By ~ 1

Author(s):

Armando Astarola ◽

Jesus Lazaro ◽

Unai Bidarte ◽

Jaime Jimenez ◽

Jagoba Arias

Keyword(s):

Motor Control ◽

Software Architecture ◽

Reconfigurable Hardware ◽

Run Time ◽

Ip Cores

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Run-Time Management of Reconfigurable Hardware Tasks Using Embedded Linux

2007 International Conference on Field-Programmable Technology ◽

10.1109/fpt.2007.4439251 ◽

2007 ◽

Cited By ~ 10

Author(s):

Krzysztof Kosciuszkiewicz ◽

Fearghal Morgan ◽

Krzysztof Kepa

Keyword(s):

Time Management ◽

Embedded Linux ◽

Reconfigurable Hardware ◽

Run Time

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Incremental elaboration for run-time reconfigurable hardware designs

Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems - CASES '06 ◽

10.1145/1176760.1176773 ◽

2006 ◽

Cited By ~ 1

Author(s):

Arran Derbyshire ◽

Tobias Becker ◽

Wayne Luk

Keyword(s):

Reconfigurable Hardware ◽

Run Time ◽

Hardware Designs

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Using Partial-Run-Time Reconfigurable Hardware to accelerate Video Processing in Driver Assistance System

2007 Design, Automation & Test in Europe Conference & Exhibition ◽

10.1109/date.2007.364642 ◽

2007 ◽

Cited By ~ 36

Author(s):

Christopher Claus ◽

Johannes Zeppenfeld ◽

Florian Muller ◽

Walter Stechele

Keyword(s):

Video Processing ◽

Driver Assistance System ◽

Reconfigurable Hardware ◽

Assistance System ◽

Driver Assistance ◽

Run Time

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A run-time reconfigurable hardware infrastructure for IP-core evaluation and test

International Conference on Field Programmable Logic and Applications, 2005. ◽

10.1109/fpl.2005.1515772 ◽

2005 ◽

Cited By ~ 2

Author(s):

R. Siripokarpirom

Keyword(s):

Reconfigurable Hardware ◽

Ip Core ◽

Run Time ◽

Core Evaluation

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Run-time reconfigurable hardware blocks for multimedia applications

Canadian Conference on Electrical and Computer Engineering, 2005. ◽

10.1109/ccece.2005.1557376 ◽

2006 ◽

Cited By ~ 1

Author(s):

N. Sakr ◽

V. Groza

Keyword(s):

Reconfigurable Hardware ◽

Multimedia Applications ◽

Run Time

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Fingerprint Image Processing Acceleration Through Run-Time Reconfigurable Hardware

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2010.2087970 ◽

2010 ◽

Vol 57 (12) ◽

pp. 991-995 ◽

Cited By ~ 34

Author(s):

M. Fons ◽

F. Fons ◽

E. Canto

Keyword(s):

Image Processing ◽

Reconfigurable Hardware ◽

Fingerprint Image ◽

Run Time

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A Bridging Layer for Run-Time Reconfigurable Hardware Operating Systems

2008 IEEE Instrumentation and Measurement Technology Conference ◽

10.1109/imtc.2008.4547112 ◽

2008 ◽

Author(s):

Ricardo Villalobos ◽

Rami Abielmona ◽

Voicu Groza

Keyword(s):

Operating Systems ◽

Reconfigurable Hardware ◽

Run Time

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Writing Portable Applications that Dynamically Bind at Run Time to Reconfigurable Hardware

15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007) ◽

10.1109/fccm.2007.39 ◽

2007 ◽

Cited By ~ 5

Author(s):

Nicholas Moore ◽

Albert Conti ◽

Miriam Leeser ◽

Laurie Smith King

Keyword(s):

Reconfigurable Hardware ◽

Run Time

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The Reduceron reconfigured and re-evaluated

Journal of Functional Programming ◽

10.1017/s0956796812000214 ◽

2012 ◽

Vol 22 (4-5) ◽

pp. 574-613 ◽

Cited By ~ 1

Author(s):

MATTHEW NAYLOR ◽

COLIN RUNCIMAN

Keyword(s):

Reconfigurable Hardware ◽

Functional Language ◽

Language Implementation ◽

Time Performance ◽

Risc Processor ◽

Dynamic Analyses ◽

Parallel Memories ◽

Run Time

AbstractA new version of a special-purpose processor for running lazy functional programs is presented. This processor – the Reduceron – exploits parallel memories and dynamic analyses to increase evaluation speed, and is implemented using reconfigurable hardware. Compared to a more conventional functional language implementation targeting a standard RISC processor running on the same reconfigurable hardware, the Reduceron offers a significant improvement in run-time performance.

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