scholarly journals An FPGA Implementation of HW/SW Codesign Architecture for H.263 Video Coding

10.5772/15469 ◽  
2011 ◽  
Author(s):  
A. Ben ◽  
P. Kadionik ◽  
F. Ghozzi ◽  
P. Nouel ◽  
N. Masmoudi ◽  
...  
Keyword(s):  
Video Coding ◽  
Fpga Implementation

An FPGA implementation of a flexible architecture for H.263 video coding

2003 ◽  
Vol 48 (4) ◽  
pp. 1056-1066 ◽  
Author(s):  
M.J. Garrido ◽  
C. Sanz ◽  
M. Jimenez ◽  
J.M. Menesses
Keyword(s):  
Video Coding ◽  
Fpga Implementation ◽  
Flexible Architecture

An FPGA implementation of HW/SW codesign architecture for H.263 video coding

2007 ◽  
Vol 61 (9) ◽  
pp. 605-620 ◽  
Author(s):  
Ahmed Ben Atitallah ◽  
Patrice Kadionik ◽  
Fahmi Ghozzi ◽  
Patrice Nouel ◽  
Nouri Masmoudi ◽  
...  
Keyword(s):  
Video Coding ◽  
Fpga Implementation

An efficient low-cost FPGA implementation of a configurable motion estimation for H.264 video coding

2012 ◽  
Vol 9 (1) ◽  
pp. 19-30 ◽  
Author(s):  
Wajdi Elhamzi ◽  
Julien Dubois ◽  
Johel Miteran ◽  
Mohamed Atri
Keyword(s):  
Motion Estimation ◽  
Video Coding ◽  
Low Cost ◽  
Fpga Implementation

scholarly journals Low Power FPGA Implementation of Multi-View Video Coding with Hybrid Compression and Decompression Algorithm

2020 ◽  
Vol 9 (3) ◽  
pp. 2395-2403
Keyword(s):  
Video Coding ◽  
Video Compression ◽  
Hybrid Algorithm ◽  
Research Work ◽  
Fpga Implementation ◽  
Computational Time ◽  
Discrete Wavelet ◽  
Compression Process ◽  
Compression Technique ◽  
Flip Flop

The video is one of the most useful and most appealing medium to represent some information. More usage of digital multi-media via communications media, wireless communications, intranet, internet and cellular mobile leads to the uncontrollable growth of data in media. The video compression technique is used in this research work to improve the processing speed of the entire system. In this work, Low Cost - Multi Video Coding - Hybrid Compression and Decompression (LC-MVC-HCD) method is used to reduce computation complexity. The combinational of Discrete Wavelet Transform (DWT) and Discrete Cosine Transform (DCT) algorithms are denoted as hybrid algorithm. Based on this hybrid algorithm, the compression process is performing which improves the video coding efficiency of MVC. The LC-MVC-HCD methodwas implemented in the Matlab, Xilinx and Cadence tool. In Application Specific Integrated Circuit (ASIC) implementation, the area, power, and delay minimized by using the cadence encounter tool with 180nm and 45nm technology. In Field Programmable Gate Array (FPGA) implementation, the number of Lookup Tables (LUTs), slice, and flip-flop are minimized based on two different kinds of Virtex devices such as Virtex -6 and Virtex-7. In Matlab, Peak Signal to Noise Ratio (PSNR), computational time and bit error rate were analyzed for the LC-MVC-HCD method. The experimental outcome showed that the proposed methodology has improved performance ASIC and FPGA up to 2-3% compared to existing methods like Direct mode decision MVC and LC-MVC-DWT.

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