scholarly journals Phase noise and jitter modeling for fractional-N PLLs

2007 ◽  
Vol 5 ◽  
pp. 313-320 ◽  
Author(s):  
S. A. Osmany ◽  
F. Herzel ◽  
K. Schmalz ◽  
W. Winkler
Keyword(s):  
Phase Noise ◽  
Phase Error ◽  
Digital Signal ◽  
Noise Model ◽  
Phase Locked Loops ◽  
Voltage Controlled Oscillator ◽  
Ofdm Systems ◽  
Loop Filter ◽  
Sigma Delta Modulator ◽  
Noise Optimization

Abstract. We present an analytical phase noise model for fractional-N phase-locked loops (PLL) with emphasis on integrated RF synthesizers in the GHz range. The noise of the crystal reference, the voltage-controlled oscillator (VCO), the loop filter, the charge pump, and the sigma-delta modulator (SDM) is filtered by the PLL operation. We express the rms phase error (jitter) in terms of phase noise of the reference, the VCO phase noise and the third-order loop filter parameters. In addition, we consider OFDM systems, where the PLL phase noise is reduced by digital signal processing after down-conversion of the RF signal to baseband. The rms phase error is discussed as a function of the loop parameters. Our model drastically simplifies the noise optimization of the PLL loop dynamics.

scholarly journals A Ku-Band Fractional-N Frequency Synthesizer with Adaptive Loop Bandwidth Control

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 109
Author(s):  
Youming Zhang ◽  
Xusheng Tang ◽  
Zhennan Wei ◽  
Kaiye Bao ◽  
Nan Jiang
Keyword(s):  
Phase Noise ◽  
Frequency Synthesizer ◽  
Frequency Tuning ◽  
Cmos Technology ◽  
Voltage Controlled Oscillator ◽  
Loop Filter ◽  
Chip Area ◽  
Loop Bandwidth ◽  
Bandwidth Control ◽  
Ku Band

This paper presents a Ku-band fractional-N frequency synthesizer with adaptive loop bandwidth control (ALBC) to speed up the lock settling process and meanwhile ensure better phase noise and spur performance. The theoretical analysis and circuits implementation are discussed in detail. Other key modules of the frequency synthesizer such as broadband voltage-controlled oscillator (VCO) with auto frequency calibration (AFC) and programable frequency divider/charge pump/loop filter are designed for integrity and flexible configuration. The proposed frequency synthesizer is fabricated in 0.13 μm CMOS technology occupying 1.14 × 1.18 mm2 area including ESD/IOs and pads, and the area of the ALBC is only 55 × 76 μm2. The out frequency can cover from 11.37 GHz to 14.8 GHz with a frequency tuning range (FTR) of 26.2%. The phase noise is −112.5 dBc/Hz @ 1 MHz and −122.4 dBc/Hz @ 3 MHz at 13 GHz carrier frequency. Thanks to the proposed ALBC, the lock-time can be shortened by about 30% from about 36 μs to 24 μs. The chip area and power consumption of the proposed ALBC technology are slight, but the beneficial effect is significant.

scholarly journals Non-Linear Mathematical Modelling for Phase Locked Loop

2018 ◽  
Vol 7 (4.10) ◽  
pp. 81
Author(s):  
Prithiviraj R ◽  
Selvakumar J
Keyword(s):  
High Speed ◽  
Linear Models ◽  
Low Cost ◽  
Phase Error ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Low Noise ◽  
Voltage Controlled Oscillator ◽  
Loop Filter ◽  
Non Linear

Design of Phase Locked Loop (PLL) plays a vital role in transceiver field. Phase Locked Loop comprises of three blocks, namely Phase and frequency detector, loop filter and voltage-controlled oscillator. The greater advancements in CMOS technology such as high frequency, high speed, low noise and phase error leads to low-cost PLL This work aims to develop higher order non-linear models of general Phase Locked Loop. The condition of stability and choice of loop filter is also determined. Based on the analysis, the transfer function for PLL is determined.  

500 kHz – 5 MHz Phase-Locked Loops in High-Temperature Silicon Carbide CMOS

2014 ◽  
Vol 2014 (HITEC) ◽  
pp. 000076-000083 ◽  
Author(s):  
Paul Shepherd ◽  
Ashfaqur Rahman ◽  
Shamim Ahmed ◽  
A Matt Francis ◽  
Jim Holmes ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
Integrated Circuits ◽  
Extreme Environments ◽  
Phase Locked Loops ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Loop Filter ◽  
Fully Integrated ◽  
Improved Performance

Silicon Carbide (SiC) integrated circuits processes show promise for improved performance in high temperature, high radiation, and other extreme environments. The circuits described are the first implementations of phase-locked or delay-locked loops in SiC. The PLL utilizes a common charge-pump topology including a fully integrated passive loop filter, and were designed with a target maximum operating frequency of 5 MHz. Component blocks use novel topologies to optimize performance in a SiC CMOS process. Experimental results of both the complete PLL as well as the Phase Frequency Detector and Voltage Controlled Oscillator components are presented. Operation of the PLL at frequencies up to 1.5 MHz is demonstrated through test results of unpackaged die.

Compensation of Phase Noise Effects for IEEE 802.16e OFDMA Systems

2011 ◽  
Vol 204-210 ◽  
pp. 1330-1335
Author(s):  
Chien Sheng Chen ◽  
Yung Chuan Lin ◽  
He Nian Shou ◽  
Chi Tien Sun
Keyword(s):  
Phase Noise ◽  
Fading Channel ◽  
Orthogonal Frequency Division Multiplexing ◽  
Phase Error ◽  
Delay Spread ◽  
Ofdm Systems ◽  
Ofdm System ◽  
Ieee 802.16E ◽  
Noise Effects ◽  
Channel One

Orthogonal frequency division multiplexing (OFDM) system which provides high spectral efficiency has obvious advantages in robustness against the multipath delay spread and the fading channel. One of the major disadvantages of such a multi-carrier modulated system is the sensitivity of its performance to synchronization error, such as phase noise and frequency offset. Phase noise is caused by the mismatch between the transmitter and the receiver oscillators. Phase noise in an OFDM system can destroy the orthogonality of the subcarriers and cause inter-carrier interference (ICI). Phase noise resulting in common phase error (CPE) and Inter-Carrier Interference is a critical challenge to the implementation of OFDM systems. In this paper, the phase noise effects of the IEEE 802.16e OFDMA systems are compensated. The practical cluster-based method which is used to estimate either the CPE or the ICI coefficients in the fading channel and compensate the effects of phase error is also proposed. Numerical results demonstrate that the proposed algorithm can effectively improve the performance caused by phase noise.

scholarly journals CMOS active inductors and transformers for wireless applications

2021 ◽  
Author(s):  
Adrian Tang
Keyword(s):  
Phase Noise ◽  
Dynamic Range ◽  
Current Mode ◽  
Voltage Controlled Oscillator ◽  
Large Signal ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Wireless Applications ◽  
Active Inductors ◽  
Active Circuit

This thesis first reviews existing work in CMOS active inductors focusing on two implementations, Wu gyrator-C and differential floating active inductors. It then proposes a new method of quantifying the performance of active inductors by introducing a figure of merit called "mean quality factor" that is better suited to the large signal behavior of active inductors. New CMOS constant-Q active inductors are proposed that are intended specifically for applications where a large signal operation in required. The thesis then proposes CMOS active transformers that are active circuit equivalents of two magnetically coupled coils. Four applications of constant-Q active inductors and active transformers namely a 2.4 GHz voltage-controlled oscillator with -119.5dBc/Hz phase noise at 1 MHz offset, a 2.4 GHz current-mode phase-locked loop with -116dBc/Hz phase noise at 1 MHz offset and 80ns lock time, a 5 MHz 100X oversampled current-mode sigma-delta modulator with 50dB dynamic range and 65dB SNR, and a 1.6 GHz QPSK phase modulator with -101dBc/Hz phase noise at 1 MHz offset are presented.

scholarly journals CMOS active inductors and transformers for wireless applications

2021 ◽  
Author(s):  
Adrian Tang
Keyword(s):  
Phase Noise ◽  
Dynamic Range ◽  
Current Mode ◽  
Voltage Controlled Oscillator ◽  
Large Signal ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Wireless Applications ◽  
Active Inductors ◽  
Active Circuit

This thesis first reviews existing work in CMOS active inductors focusing on two implementations, Wu gyrator-C and differential floating active inductors. It then proposes a new method of quantifying the performance of active inductors by introducing a figure of merit called "mean quality factor" that is better suited to the large signal behavior of active inductors. New CMOS constant-Q active inductors are proposed that are intended specifically for applications where a large signal operation in required. The thesis then proposes CMOS active transformers that are active circuit equivalents of two magnetically coupled coils. Four applications of constant-Q active inductors and active transformers namely a 2.4 GHz voltage-controlled oscillator with -119.5dBc/Hz phase noise at 1 MHz offset, a 2.4 GHz current-mode phase-locked loop with -116dBc/Hz phase noise at 1 MHz offset and 80ns lock time, a 5 MHz 100X oversampled current-mode sigma-delta modulator with 50dB dynamic range and 65dB SNR, and a 1.6 GHz QPSK phase modulator with -101dBc/Hz phase noise at 1 MHz offset are presented.

Extension of the LTV Phase Noise Model of Electrical Oscillators for the Output Harmonics

2012 ◽  
Vol E95.C (12) ◽  
pp. 1846-1856 ◽  
Author(s):  
Seyed Amir HASHEMI ◽  
Hassan GHAFOORIFARD ◽  
Abdolali ABDIPOUR
Keyword(s):  
Phase Noise ◽  
Noise Model ◽  
Electrical Oscillators

Power Efficient Implementation of Low Noise CMOS LC VCO using 32nm Technology for RF Applications

2018 ◽  
Vol 6 (8) ◽  
pp. 53
Author(s):  
Shitesh Tiwari ◽  
Sumant Katiyal ◽  
Parag Parandkar
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Tuning Range ◽  
Low Voltage ◽  
Performance Comparison ◽  
Low Noise ◽  
Center Frequency ◽  
Voltage Controlled Oscillator ◽  
Low Phase Noise ◽  
Lc Vco

Voltage Controlled Oscillator (VCO) is an integral component of most of the receivers such as GSM, GPS etc. As name indicates, oscillation is controlled by varying the voltage at the capacitor of LC tank. By varying the voltage, VCO can generate variable frequency of oscillation. Different VCO Parameters are contrasted on the basis of phase noise, tuning range, power consumption and FOM. Out of these phase noise is dependent on quality factor, power consumption, oscillation frequency and current. So, design of LC VCO at low power, low phase noise can be obtained with low bias current at low voltage.  Nanosize transistors are also contributes towards low phase noise. This paper demonstrates the design of low phase noise LC VCO with 4.89 GHz tuning range from 7.33-11.22 GHz with center frequency at 7 GHz. The design uses 32nm technology with tuning voltage of 0-1.2 V. A very effective Phase noise of -114 dBc / Hz is obtained with FOM of -181 dBc/Hz. The proposed work has been compared with five peer LC VCO designs working at higher feature sizes and outcome of this performance comparison dictates that the proposed work working at better 32 nm technology outperformed amongst others in terms of achieving low Tuning voltage and moderate FoM, overshadowed by a little expense of power dissipation. 

Sign in / Sign up

Export Citation Format

Share Document