Survey on Power Optimization Techniques for Low PowerVLSI Circuitsin Deep Submicron Technology

Suguna T; Janaki Rani M

doi:10.5121/vlsic.2018.9101

Survey on Power Optimization Techniques for Low PowerVLSI Circuitsin Deep Submicron Technology

International Journal of VLSI Design & Communication Systems ◽

10.5121/vlsic.2018.9101 ◽

2018 ◽

Vol 9 (1) ◽

pp. 01-15

Author(s):

Suguna T ◽

Janaki Rani M

Keyword(s):

Power Optimization ◽

Deep Submicron ◽

Optimization Techniques

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Power Optimization Techniques for Deep Submicron Devices

Journal of Nanoelectronics and Optoelectronics ◽

10.1166/jno.2013.1483 ◽

2013 ◽

Vol 8 (4) ◽

pp. 383-389

Author(s):

S. Senthilrani ◽

M. Suganthi

Keyword(s):

Power Optimization ◽

Deep Submicron ◽

Optimization Techniques ◽

Submicron Devices

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Power Optimization Opportunities for a Reconfigurable Arithmetic Component in the Deep Submicron Domain

2012 15th Euromicro Conference on Digital System Design ◽

10.1109/dsd.2012.105 ◽

2012 ◽

Author(s):

Dimitris Bekiaris ◽

George Economakos

Keyword(s):

Power Optimization ◽

Deep Submicron

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Power Optimization Techniques for DDR3 SDRAM

2015 28th International Conference on VLSI Design ◽

10.1109/vlsid.2015.59 ◽

2015 ◽

Author(s):

Preeti Ranjan Panda ◽

Vishal Patel ◽

Praxal Shah ◽

Namita Sharma ◽

Vaidyanathan Srinivasan ◽

...

Keyword(s):

Power Optimization ◽

Optimization Techniques

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Statistical power optimization of deep-submicron digital CMOS circuits based on structured perceptron

2014 International Symposium on Integrated Circuits (ISIC) ◽

10.1109/isicir.2014.7029446 ◽

2014 ◽

Author(s):

Amir Zjajo ◽

Nick van der Meijs ◽

Rene van Leuken

Keyword(s):

Statistical Power ◽

Power Optimization ◽

Deep Submicron ◽

Cmos Circuits ◽

Digital Cmos

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Power Optimization Techniques for Multicore SoCs

Multicore Systems On-Chip: Practical Software/Hardware Design - Atlantis Ambient and Pervasive Intelligence ◽

10.2991/978-94-91216-92-3_8 ◽

2013 ◽

pp. 175-193

Author(s):

Abderazek Ben Abdallah

Keyword(s):

Power Optimization ◽

Optimization Techniques

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Power Optimization Techniques

Low-Power CMOS Design ◽

10.1109/9780470545058.sect14 ◽

2009 ◽

Keyword(s):

Power Optimization ◽

Optimization Techniques

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Power Optimization Techniques for High-Level Designs Using Multiple Voltage Components for Low Power Consumption

Journal of Low Power Electronics ◽

10.1166/jolpe.2018.1547 ◽

2018 ◽

Vol 14 (2) ◽

pp. 275-284

Author(s):

Khushbu Chandrakar ◽

Sudeshna Kundu ◽

Suchismita Roy

Keyword(s):

Power Consumption ◽

Low Power ◽

Power Optimization ◽

Optimization Techniques ◽

Low Power Consumption ◽

High Level

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Leakage power optimization techniques for ultra deep sub-micron multi-level caches

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486) ◽

10.1109/iccad.2003.1257876 ◽

2004 ◽

Author(s):

Nam Sung Kim ◽

D. Blaauw ◽

T. Mudge

Keyword(s):

Power Optimization ◽

Leakage Power ◽

Optimization Techniques ◽

Multi Level

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TAPO: Thermal-aware power optimization techniques for servers and data centers

2011 International Green Computing Conference and Workshops ◽

10.1109/igcc.2011.6008610 ◽

2011 ◽

Cited By ~ 29

Author(s):

Wei Huang ◽

Malcolm Allen-Ware ◽

John B. Carter ◽

Elmootazbellah Elnozahy ◽

Hendrik Hamann ◽

...

Keyword(s):

Data Centers ◽

Power Optimization ◽

Optimization Techniques

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Power Optimization Techniques for Sequential Elements Using Pulse Triggered Flip-Flops with SVL Logic

IOSR Journal of VLSI and Signal processing ◽

10.9790/4200-0143136 ◽

2012 ◽

Vol 1 (4) ◽

pp. 31-36

Author(s):

A. Jagadeeswaran

Keyword(s):

Power Optimization ◽

Optimization Techniques

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