Optimal Unate Decomposition Method for Synthesis of Mixed CMOS VLSI Circuits

Sai Praveen Kadiyala; Debasis Samanta

doi:10.5121/vlsic.2016.7201

Optimal Unate Decomposition Method for Synthesis of Mixed CMOS VLSI Circuits

International Journal of VLSI Design & Communication Systems ◽

10.5121/vlsic.2016.7201 ◽

2016 ◽

Vol 7 (2) ◽

pp. 01-19

Author(s):

Sai Praveen Kadiyala ◽

Debasis Samanta

Keyword(s):

Decomposition Method ◽

Vlsi Circuits ◽

Cmos Vlsi

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An approach to crosstalk effect analysis and avoidance techniques in digital CMOS VLSI circuits

International Journal of Electronics ◽

10.1080/00207218808945198 ◽

1988 ◽

Vol 65 (1) ◽

pp. 9-17 ◽

Cited By ~ 26

Author(s):

R. ANGLADA ◽

A. RUBIO

Keyword(s):

Vlsi Circuits ◽

Digital Cmos ◽

Effect Analysis ◽

Cmos Vlsi

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Reliability in CMOS VLSI circuits

[1991 Proceedings] The Twenty-Third Southeastern Symposium on System Theory ◽

10.1109/ssst.1991.138558 ◽

2002 ◽

Author(s):

P. Kukkal ◽

J. Bowles

Keyword(s):

Vlsi Circuits ◽

Cmos Vlsi

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Test generation for current testing of bridging faults in CMOS VLSI circuits

38th Midwest Symposium on Circuits and Systems. Proceedings ◽

10.1109/mwscas.1995.504443 ◽

2002 ◽

Cited By ~ 1

Author(s):

T. Lee ◽

I.N. Hajj

Keyword(s):

Test Generation ◽

Vlsi Circuits ◽

Bridging Faults ◽

Current Testing ◽

Cmos Vlsi

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A built-in quiescent current monitor for CMOS VLSI circuits

Proceedings the European Design and Test Conference. ED&TC 1995 ◽

10.1109/edtc.1995.470341 ◽

2002 ◽

Cited By ~ 13

Author(s):

A. Rubio ◽

E. Janssens ◽

H. Casier ◽

J. Figueras ◽

D. Mateo ◽

...

Keyword(s):

Vlsi Circuits ◽

Quiescent Current ◽

Cmos Vlsi

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A crosstalk sensor implementation for measuring interferences in digital CMOS VLSI circuits

Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646) ◽

10.1109/olt.2000.856611 ◽

2002 ◽

Cited By ~ 4

Author(s):

J.A. Sainz ◽

M. Roca ◽

R. Munoz ◽

J.A. Maiz ◽

L.A. Aguado

Keyword(s):

Vlsi Circuits ◽

Digital Cmos ◽

Cmos Vlsi

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Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.402499 ◽

1995 ◽

Vol 14 (8) ◽

pp. 998-1012 ◽

Cited By ~ 107

Author(s):

H. Kriplani ◽

F.N. Najm ◽

I.N. Hajj

Keyword(s):

Vlsi Circuits ◽

Current Estimation ◽

Maximum Current ◽

Cmos Vlsi

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Back propagation neural network based power estimation method for CMOS VLSI circuits

10.1063/5.0070733 ◽

2022 ◽

Author(s):

V. Govindaraj ◽

B. Shoban Babu ◽

C. Ezhilazhagan

Keyword(s):

Neural Network ◽

Back Propagation ◽

Estimation Method ◽

Power Estimation ◽

Back Propagation Neural Network ◽

Vlsi Circuits ◽

Cmos Vlsi

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Stochastic methods for transistor size optimization of CMOS VLSI circuits

Parallel Problem Solving from Nature — PPSN IV - Lecture Notes in Computer Science ◽

10.1007/3-540-61723-x_1048 ◽

1996 ◽

pp. 849-858 ◽

Cited By ~ 5

Author(s):

Robert Rogenmoser ◽

Hubert Kaeslin ◽

Tobias Blickle

Keyword(s):

Vlsi Circuits ◽

Stochastic Methods ◽

Size Optimization ◽

Cmos Vlsi

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Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits

IEICE Transactions on Electronics ◽

10.1093/ietele/e88-c.4.509 ◽

2005 ◽

Vol E88-C (4) ◽

pp. 509-519 ◽

Cited By ~ 151

Author(s):

F. FALLAH

Keyword(s):

Leakage Current ◽

Current Control ◽

Vlsi Circuits ◽

Cmos Vlsi

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Leakage Power Reduction in CMOS VLSI Circuits

International Journal of Computer Applications ◽

10.5120/8778-2721 ◽

2012 ◽

Vol 55 (8) ◽

pp. 42-48 ◽

Cited By ~ 11

Author(s):

Pushpa Saini ◽

Rajesh Mehra

Keyword(s):

Power Reduction ◽

Leakage Power ◽

Vlsi Circuits ◽

Cmos Vlsi

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