scholarly journals Design of 2.4 Ghz Mmic Feed Forward Amplifier for Wireless Applications

2019 ◽  
Vol 05 (02) ◽  
pp. 01-07
Author(s):  
Shanthi P ◽  
Baligar JS
Keyword(s):  
Feed Forward ◽  
Wireless Applications

A LOW POWER CASCADED FEED-FORWARD DELTA-SIGMA MODULATOR FOR RF WIRELESS APPLICATIONS

2009 ◽  
Vol 18 (02) ◽  
pp. 407-429 ◽  
Author(s):  
SHAILESH B. NERURKAR ◽  
KHALID H. ABED
Keyword(s):  
Power Consumption ◽  
Cmos Technology ◽  
Third Order ◽  
Feed Forward ◽  
Analog To Digital ◽  
Wireless Applications ◽  
Fully Differential ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Rf Wireless

This paper presents a design of a novel cascaded third-order feed-forward delta-sigma analog-to-digital converter (ADC). This ADC is realized using fully differential switched capacitor architecture and produces a 12-bit resolution at a data output rate (DOR) of 2.5 MS/s for RF wireless applications. The delta-sigma modulator consists of a second-order single-bit feed-forward modulator cascaded with a multi-bit first-order modulator. The cascaded feed-forward third-order (2-1) ADC is simulated using Matlab and Simulink. The delta-sigma modulator was designed using Cadence Virtuoso in TSMC 0.18 μm CMOS technology. The power consumption of the designed modulator is 12.74 mW, and the resolution is 11.85 bits for an over-sampling ratio (M = 32). The figure of merit is 1.38 pJ at a sample rate of 80 MS/s. The proposed delta-sigma modulator is compared with other state-of-the-art low-pass delta-sigma modulators in terms of their speed, power, DOR, and the proposed modulator has one of the lowest power consumption.

A Feed-Forward Time Amplifier Using a Phase Detector and Variable Delay Lines

2013 ◽  
Vol E96.C (6) ◽  
pp. 920-922 ◽  
Author(s):  
Kiichi NIITSU ◽  
Naohiro HARIGAI ◽  
Takahiro J. YAMAGUCHI ◽  
Haruo KOBAYASHI
Keyword(s):  
Phase Detector ◽  
Variable Delay ◽  
Delay Lines ◽  
Feed Forward ◽  
Time Amplifier
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