scholarly journals On Optimization of Manufacturing of a Conventional Folded Cascode Operational Amplifier Based on Heterostructures to Increase Density of their Elements. Influence of Missmatch Induced Stress and Porosity of Materials on Technological Process

2018 ◽  
Vol 7 (2) ◽  
pp. 01-19
Author(s):  
Pankratov E.L
Keyword(s):  
Technological Process ◽  
Operational Amplifier ◽  
Induced Stress ◽  
Folded Cascode

A 1-mm2 CMOS-pipelined ADC with integrated folded cascode operational amplifier

2020 ◽  
Vol 37 (4) ◽  
pp. 205-213
Author(s):  
Norhamizah Idros ◽  
Zulfiqar Ali Abdul Aziz ◽  
Jagadheswaran Rajendran
Keyword(s):  
Operational Amplifier ◽  
Open Loop ◽  
Cmos Process ◽  
Silicon Area ◽  
Content Type ◽  
Op Amp ◽  
Dc Gain ◽  
Input Range ◽  
Folded Cascode ◽  
The Impact

Purpose The purpose of this paper is to demonstrate the acceptable performance by using the limited input range towards lower open-loop DC gain operational amplifier (op-amp) of an 8-bit pipelined analog-to-digital converter (ADC) for mobile communication application. Design/methodology/approach An op-amp with folded cascode configuration is designed to provide the maximum open-loop DC gain without any gain-boosting technique. The impact of low open-loop DC gain is observed and analysed through the results of pre-, post-layout simulations and measurement of the ADC. The fabrication process technology used is Silterra 0.18-µm CMOS process. The silicon area by the ADC is 1.08 mm2. Findings Measured results show the differential non-linearity (DNL) error, integral non-linearity (INL) error, signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) are within −0.2 to +0.2 LSB, −0.55 LSB for 0.4 Vpp input range, 22 and 27 dB, respectively, with 2 MHz input signal at the rate of 64 MS/s. The static power consumption is 40 mW with a supply voltage of 1.8 V. Originality/value The experimental results of ADC showed that by limiting the input range to ±0.2 V, this ADC is able to give a good reasonable performance. Open-loop DC gain of op-amp plays a critical role in ADC performance. Low open-loop DC gain results in stage-gain error of residue amplifier and, thus, leads to nonlinearity of output code. Nevertheless, lowering the input range enhances the linearity to ±0.2 LSB.

scholarly journals Design of Analog Signal Processing Applications Using Carbon Nanotube Field Effect Transistor-Based Low-Power Folded Cascode Operational Amplifier

2018 ◽  
Vol 2018 ◽  
pp. 1-15 ◽  
Author(s):  
Varsha S. Bendre ◽  
A. K. Kureshi ◽  
Saurabh Waykole
Keyword(s):  
Signal Processing ◽  
Carbon Nanotube ◽  
Low Power ◽  
Operational Amplifier ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Analog Signal Processing ◽  
Analog Signal ◽  
Zero Crossing ◽  
Folded Cascode

Carbon nanotube (CNT) is one of the embryonic technologies within recent inventions towards miniaturization of semiconductor devices and is gaining much attention due to very high throughput and very extensive series of applications in various analog/mixed signal applications of today’s high-speed era. The carbon nanotube field effect transistors (CNFETs) have been reconnoitred as the stimulating aspirant for the future generations of integrated circuit (IC) devices. CNFETs are being widely deliberated as probable replacement to silicon MOSFETs also. In this paper, different analog signal processing applications such as inverting amplifier, noninverting amplifier, summer, subtractor, differentiator, integrator, half-wave and full-wave rectifiers, clipper, clamper, inverting and noninverting comparators, peak detector, and zero crossing detector are implemented using low-power folded cascode operational amplifier (op-amp) implemented using CNFET. The proposed CNFET-based analog signal processing applications are instigated at 32 nm technology node. Simulation results show that the proposed applications are properly implemented using novel folded cascode operational amplifier (FCOA) implemented using CNFET.

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