scholarly journals Estimation of Optimized Energy and Latency Constraint for Task Allocation in 3d Network on Chip

2014 ◽  
Vol 6 (2) ◽  
pp. 67-86
Author(s):  
Vaibhav Jha ◽  
Mohit Jha ◽  
G K Sharma
Keyword(s):  
Task Allocation ◽  
Network On Chip ◽  
3D Network ◽  
On Chip

Designing 2D and 3D Network-on-Chip Architectures

2014 ◽  
Author(s):  
Konstantinos Tatas ◽  
Kostas Siozios ◽  
Dimitrios Soudris ◽  
Axel Jantsch
Keyword(s):  
Network On Chip ◽  
3D Network ◽  
On Chip ◽  
2D And 3D

Power-and Thermal-aware Mapping for 3D Network-on-chip

2013 ◽  
Vol 12 (23) ◽  
pp. 7297-7304 ◽  
Author(s):  
Ge Fen ◽  
Feng Gui ◽  
Yu Shuang ◽  
Wu Ning
Keyword(s):  
Network On Chip ◽  
3D Network ◽  
On Chip

Low Temperature Direct Bond Technology for 3D Microelectronics Integration and Wafer Scale Packaging

2010 ◽  
Vol 2010 (1) ◽  
pp. 000015-000022
Author(s):  
Paul Enquist
Keyword(s):  
Low Temperature ◽  
Sensor Arrays ◽  
Cost Savings ◽  
Image Sensor ◽  
Network On Chip ◽  
Wafer Scale ◽  
Direct Bond ◽  
3D Network ◽  
On Chip ◽  
3D Volume

3D microelectronics integration and wafer scale packaging promise improvements in functional density and cost compared to conventional 2D microelectronics and packaging technologies. The realization of these improvements will require further adoption of 3D volume manufacturing process technologies. These process technologies will likely include through silicon via (TSV) and die or wafer bonding with and without 3D interconnect. Low temperature direct bond technologies have a number of inherent performance and cost advantages compared to other bonding technologies. This paper describes low temperature direct oxide bond technologies with and without a scalable 3D interconnect developed by Ziptronix and cost savings, performance and applications that will be enabled by adoption of these technologies. Enabled cost savings and performance include system or network-on-chip, system in package, and TSVs. Enabled applications include backside illuminated image sensors, micron-scale pitch vertically integrated image sensor arrays, 3D system-on-chip and 3D network-on-chip.

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