scholarly journals Non-Destructive Vector Fault Locator to Detect Resistive Open Defects in Static Random Access Memory with Improved Performance

2021 ◽  
Vol 23 (07) ◽  
pp. 667-677
Author(s):  
Madan Mali ◽  
◽  
Sheetal Tak-Barekar ◽  
Keyword(s):  
Supply Voltage ◽  
Early Stage ◽  
High Reliability ◽  
Semiconductor Industry ◽  
Random Access ◽  
Advanced Technology ◽  
Test Time ◽  
Slight Variation ◽  
Improved Performance ◽  
Resistive Defects

The efforts in the semiconductor industry lead to the up-gradation of device size and performance of the devices. Extensive use of cache memory with significant size has become the requirement of most devices, applications, and gadgets. Advanced nanotechnology has resulted in scaled devices and more components with complex circuitry on system-on-chip. The memories are placed incredibly more profound in the die, and memory pins are not accessible readily, leading to more complications in testing the memories. The manufacturing of scaled devices is also a challenging task. A slight variation in doping concentration or process, supply voltage, temperature variations leads to faults in the memory. Advanced technology has increased the possibilities of occurrences of resistive defects in memories. For the smooth operation of systems with high reliability, it is essential to detect all the defects in the memory. In this paper, the detection of resistive defects is proposed at an early stage to increase the life span of the memory cells. Feeble cell detected at an early stage inhibits the more mutilation of the cells and improves memory reliability. An extensive range of defective values is used to analyze the proposed method to cover all positions of the defects in the cell. The proposed method detects the resistive defects with a minimum test time of 81.95μs for 4KB of the memory and contributes a negligible area overhead of 0.77%.

Ru Passivated and Ru Doped e-TaN surfaces as Combined Barrier and Liner Material for Copper Interconnects: A First Principles Study

2018 ◽  
Author(s):  
Suresh Natarajan ◽  
Cara-Lena Nies ◽  
Michael Nolan
Keyword(s):  
First Principles ◽  
Film Growth ◽  
Early Stage ◽  
Copper Interconnects ◽  
Liner Material ◽  
Critical Dimensions ◽  
Industry Standard ◽  
Cu Film ◽  
Improved Performance ◽  
And Diffusion

<div>As the critical dimensions of transistors continue to be scaled down to facilitate improved performance and device speeds, new ultrathin materials that combine diffusion barrier and seed/liner properties are needed for copper interconnects at these length scales. Ideally, to facilitate coating of high aspect ratio structures, this alternative barrier+liner material should only consist of one or as few layers as possible. We studied TaN, the current industry standard for Cu diffusion barriers, and Ru, which is a</div><div>suitable liner material for Cu electroplating, to explore how combining these two materials in a barrier+liner material influences the adsorption of Cu atoms in the early stage of Cu film growth. To this end, we carried out first-principles simulations of the adsorption and diffusion of Cu adatoms at Ru-passivated and Ru-doped e-TaN(1 1 0) surfaces. For comparison, we also studied the behaviour of Cu and Ru adatoms at the low index surfaces of e-TaN, as well as the interaction of Cu adatoms with the (0 0 1) surface of hexagonal Ru. Our results confirm the barrier and liner properties of TaN and Ru, respectively while also highlighting the weaknesses of both materials. Ru passivated TaN was found to have improved binding with Cu adatoms as compared to the bare TaN and Ru surfaces.</div><div>On the other hand, the energetic barrier for Cu diffusion at Ru passivated TaN surface was lower than at the bare TaN surface which can promote Cu agglomeration. For Ru-doped TaN however, a decrease in Cu binding energy was found in addition to favourable migration of the Cu adatoms toward the doped Ru atom and unfavourable migration away from it or into the bulk. This suggests that Ru doping sites in the TaN surface can act as nucleation points for Cu growth with high migration barrier preventing agglomeration and allow electroplating of Cu. Therefore Ru-doped TaN is proposed as a candidate for a combined barrier+liner material with reduced thickness.</div>

Comparative Assessment of Optical Techniques for Semi-Invasive SRAM Data Read-out on an MSP430 Microcontroller

2018 ◽  
Author(s):  
Tuba Kiyan ◽  
Heiko Lohrke ◽  
Christian Boit
Keyword(s):  
Supply Voltage ◽  
Photon Emission ◽  
Random Access ◽  
Integration Time ◽  
Security Evaluation ◽  
Testing And Debugging ◽  
Advantages And Disadvantages ◽  
The Core ◽  
Voltage Signal ◽  
Chip Testing

Abstract This paper compares the three major semi-invasive optical approaches, Photon Emission (PE), Thermal Laser Stimulation (TLS) and Electro-Optical Frequency Mapping (EOFM) for contactless static random access memory (SRAM) content read-out on a commercial microcontroller. Advantages and disadvantages of these techniques are evaluated by applying those techniques on a 1 KB SRAM in an MSP430 microcontroller. It is demonstrated that successful read out depends strongly on the core voltage parameters for each technique. For PE, better SNR and shorter integration time are to be achieved by using the highest nominal core voltage. In TLS measurements, the core voltage needs to be externally applied via a current amplifier with a bias voltage slightly above nominal. EOFM can use nominal core voltages again; however, a modulation needs to be applied. The amplitude of the modulated supply voltage signal has a strong effect on the quality of the signal. Semi-invasive read out of the memory content is necessary in order to remotely understand the organization of memory, which finds applications in hardware and software security evaluation, reverse engineering, defect localization, failure analysis, chip testing and debugging.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

An Automated Progress Tracking System for Industrial Facility Construction Projects

2013 ◽  
Vol 671-674 ◽  
pp. 2973-2977
Author(s):  
Jaeh Yun Choi ◽  
Kyu Sung Lee
Keyword(s):  
Information System ◽  
Project Management ◽  
Construction Industry ◽  
Construction Projects ◽  
Early Stage ◽  
Tracking System ◽  
Advanced Technology ◽  
Industrial Plant ◽  
Stage Of Development ◽  
Facility Construction

As amount of information in construction industry is growing, the role of information system in project management is becoming increasingly important. With the emerging IT application to the advancing construction industry, construction project management system with advanced technology has been progressed vigorously to improve construction productivity and management efficiency. Recently, a web-based Project Management Information System (PMIS) is developed to support decision-making process by efficiently managing project related information generated from various discipline. Many firms are in the process of developing the PMIS system or already have been applied the system to various projects. However, PMIS is still in its early stage of development to be applied at industrial plant construction projects. With the complexity of the industrial plant projects, the industry practitioners need to be able to visualize the construction schedule information to manage the project efficiently. This study suggests methodologies for improving PMIS specialized for industrial plant piping construction projects to estimate the baseline schedule and performance measurement more accurately by developing a framework for the piping construction projects. By using this developed system, the researchers expect that piping construction projects will be more efficiently managed on a real-time basis through measuring progress of piping at each and every state of progress milestone and provide management with opportunities to forecast the level of efforts required to execute the remaining work scope in a timely manner.

scholarly journals Digital Screening for Cognitive Impairment – A Proof of Concept Study

2021 ◽  
pp. 1-8
Author(s):  
V. Bloniecki ◽  
G. Hagman ◽  
M. Ryden ◽  
M. Kivipelto
Keyword(s):  
Cognitive Impairment ◽  
Neurodegenerative Disorder ◽  
Early Stage ◽  
Roc Curves ◽  
University Hospital ◽  
Cognitive Test ◽  
Test Time ◽  
Proof Of Concept ◽  
Cognitive Screening ◽  
Disease Modifying Drugs

Background: Due to an ageing demographic and rapid increase of cognitive impairment and dementia, combined with potential disease-modifying drugs and other interventions in the pipeline, there is a need for the development of accurate, accessible and efficient cognitive screening instruments, focused on early-stage detection of neurodegenerative disorders. Objective: In this proof of concept report, we examine the validity of a newly developed digital cognitive test, the Geras Solutions Cognitive Test (GCST) and compare its accuracy against the Montreal Cognitive Assessment (MoCA). Methods: 106 patients, referred to the memory clinic, Karolinska University Hospital, due to memory complaints were included. All patients were assessed for presence of neurodegenerative disorder in accordance with standard investigative procedures. 66% were diagnosed with subjective cognitive impairment (SCI), 25% with mild cognitive impairment (MCI) and 9% fulfilled criteria for dementia. All patients were administered both MoCA and GSCT. Descriptive statistics and specificity, sensitivity and ROC curves were established for both test. Results: Mean score differed significantly between all diagnostic subgroups for both GSCT and MoCA (p<0.05). GSCT total test time differed significantly between all diagnostic subgroups (p<0.05). Overall, MoCA showed a sensitivity of 0.88 and specificity of 0.54 at a cut-off of <=26 while GSCT displayed 0.91 and 0.55 in sensitivity and specificity respectively at a cut-off of <=45. Conclusion: This report suggests that GSCT is a viable cognitive screening instrument for both MCI and dementia.

scholarly journals Augmented Leadframe Design for Stable Multi-Wire Ground Bonding

2021 ◽  
pp. 1-5
Author(s):  
Frederick Ray I. Gomez ◽  
Alyssa Grace S. Gablan ◽  
Anthony R. Moreno ◽  
Nerie R. Gomez
Keyword(s):  
Failure Modes ◽  
High Reliability ◽  
Semiconductor Industry ◽  
Global Market ◽  
Design Solution ◽  
Package Design ◽  
Strict Compliance ◽  
Bridge Type ◽  
Major Application ◽  
Augmented Design

Technological change has brought the global market into broad industrialization and modernization. One major application in the semiconductor industry demands safety and high reliability with strict compliance requirement. This technical paper focuses on the package design solution of quad-flat no leads (QFN) to mitigate the leadframe bouncing and its consequent effect of lifted wire and/or non-stick on leads (NSOL) defects on multi-wire ground connection. Multi-wire on single lead ground (or simply Gnd) connection plays critical attribute in the test coverage risk assessment. Cases of missing wire and/or NSOL on the multi-wire Gnd connection cannot be detected at test resulting to Bin1 (good) instead of Bin5 (open) failure. To ease the failure modes mechanism, a new design of QFN leadframe package with lead-to-diepad bridge-type connection was conceptualized for device with extended leads and with multiple Gnd wires connection. The augmented design would provide better stability than the existing leadframe configurations during wirebonding. Ultimately, the design would help eliminate potential escapees at test of lifted Gnd wire not detected.

Embedded SIP Modules for next-GEN Heterogeneous “POWER-Devices”

2019 ◽  
Vol 2019 (DPC) ◽  
pp. 000383-000407
Author(s):  
Kevin Moody ◽  
Nick Stukan
Keyword(s):  
Supply Chain ◽  
Business Models ◽  
High Reliability ◽  
Semiconductor Industry ◽  
Thermal Dissipation ◽  
System Level ◽  
Electrical Performance ◽  
Power Devices ◽  
Embedded Technology ◽  
New Device

In this paper will focus on the comprehension of System-in-Package (SiP) with embedded active and passive components integration will be described. Embedding of semiconductor chips into substrates provides many advantages that have been noted. It allows the smallest package form-factor with high degree of miniaturization through sequentially stacking of multiple layers containing embedded devices that are optimized for electrical performance with short and geometrically well controlled copper interconnects. In addition, the embedding gives a homogeneous mechanical environment of the chips, resulting in good reliability at system level. Furthermore, embedded technology is an excellent resolution to Power management challenges dealing with new device technologies (Si, GaS, GaN) and optimization on the thermal dissipation with improved efficiency. Embedded technology comes with many challenges in 2019, primarily design for manufacturability (DFM) and maturity. Customers are looking for better-performance capability and pricing normally that means same or lower than die free package cost (DFPC) comparison. This paper will discuss the challenges bring to market the Embedded SIP Modules for next-GEN Heterogeneous “POWER-Devices” Today, the embedded process is being developed by printed circuit board (PCB) manufacturers creating a new supply chain, bringing new players into the semiconductor industry. This new supply chain comes along with new business models. As a result of the increasing interest in implementing embedding technologies, ACCESS Semiconductors in China is committed to be a leader in the adaptation of embedding technologies, with over 10-yrs mature coreless technology and proved design rules for low profile dimensions with seamless Ti/Cu sputtering and Cu pillar interconnect giving advantages in both electrical & power performance. ACCESS Patented “Via-in-Frame” technology provides High Reliability (MSL1, PCT, BHAST) at Cost Effective in high panel utilization for HVM, using standard substrate/PCB known material sets, no need for wafer bumping/RDL, over-mold or under-fill cost adders. ACCESS Semiconductors is currently in HVM on single die 2L, and LVM on multi-devices actives/passives 4L SiP construction both platforms are driven from the power market segment. In-development on Die Last & Frameless (MeSiP) platforms utilizing hybrid technology (mSAP) and Photo Imageable Dielectric (PID) materials for cost down solutions in HVM by Q1FY2020. Also, ACCESS Semiconductors total turn-key solutions will include front-of-line (FOL) and end-of-line (EOL) capability from wafer handling, back-grinding, and dicing with KGD traceability thru the embedded chip process, frame/strip singulation, FT, marking pack & ship providing additional 30% cost reduction in the future. Here's an illustration of Embedded Technology Roadmap and Product Platforms.

3D Technology Applications Market Trends & Key Challenges

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 000363-000400
Author(s):  
Thibault Buisson ◽  
Amandine Pizzagalli ◽  
Eric Mounier ◽  
Rozalia Beica
Keyword(s):  
Supply Chain ◽  
Business Models ◽  
Semiconductor Industry ◽  
High Volume ◽  
Advanced Technology ◽  
Passive Component ◽  
Process Technology ◽  
3D Integration ◽  
3D Technology ◽  
Major Player

Semiconductor industry, for more than four decades, has rigorously followed Moore's Law in scaling down the CMOS technologies. Although several new materials and processes are being developed to address the challenges of future technology nodes, in the coming years they will be limited with respect to functionalities that future devices will require. As a consequence a clear trend of moving from CMOS to package and system architecture can be observed. Three-dimensional (3D) technology using the well-known Through Silicon Via (TSV) interconnect is one the emerging option, considered today the most advanced technology, that could enable various heterogeneous integration. Indeed such technology is not limited to the CMOS scaling in itself, it is rather based on bringing more functionalities by stacking different type of devices (Logic, Memory, Analog, MEMS, Passive component...) while reducing the form factor of the packaging. This functional diversification is also known as More-than-Moore. In addition, considering Known Good Die approach, each component of the 3D package could have a different manufacturer using different wafer sizes and node technology, thus bringing more complexity but also more opportunities and responsibilities to the supply chain. There are several business models identified, either using vertical integration or collaborative approach, if a dominant one will emerge or several tactics will co-exist, it is still remains a key question that need to be answered. The supply chain interaction and key players will be addressed in this presentation, including current and future standardization needs. This is today a key for the manufacturing of advanced 3D devices. 3D integration is considered today a new paradigm for the semiconductor industry, since it will drive evolution for packages for the coming decades. Due to several advantages that TSV technology can bring, several platforms have started. 3D WLCSP, 2.5D interposers & 3DIC are the main platforms that will be studied in this paper. Market forecasts in terms of wafer starts, market revenue, segments and end-products as well as supply chain activities and major player interactions will be presented. The industry has enthusiastically been waiting for mass production of 3D ICs. Although some small level of production has already been reported, the adoption rate in high volume manufacturing (HVM) is still low due to unresolved challenges that the industry still needs to address. Process technology is not fully mature, there are still many challenges in bonding and de-bonding, testing as well as thermal management that have to be overcome. Furthermore, design tools have to be fully released to enable proper 3D integration design. Looking at the time to market it is foreseen that device such as the Hybrid Memory Cube, combining high-speed logic with a multiple stacks of TSV bonded memories, will come into high volume production in 2014. This will definitely change the world of the memory market and will significantly speed up the adoption of 3D technologies. Technology roadmaps for 3D integration will also be included in the manuscript and reviewed during the presentation.

The Growth of Advanced Packaging: An Overview of the Latest Technology Developments, Applications and Market Trends

2015 ◽  
Vol 2015 (1) ◽  
pp. 000001-000005 ◽  
Author(s):  
R. Beica ◽  
A. Ivankovic ◽  
T. Buisson ◽  
S. Kumar ◽  
J. Azemar
Keyword(s):  
Semiconductor Industry ◽  
Cost Effective ◽  
Cmos Technology ◽  
Advanced Technology ◽  
Current Trends ◽  
Advanced Packaging ◽  
Scaling Process ◽  
Market Trends ◽  
The Cost ◽  
Technology Nodes

The semiconductor industry, for more than five decades, has followed Moore's law and was driven by miniaturization of the transistors, scaling the CMOS technology to smaller and more advanced technology nodes while, at the same time, reducing the cost. The industry is reaching now limitations in continuing this scaling process in cost effective way. While technology nodes continue to be developed and innovative solutions are being proposed, the investment required to bring such technologies to production are significantly increasing. To overcome these limitations, new packaging technologies have been developed, enabling integration of more performing as well as various type of devices within the same package. This paper will provide an overview of current trends seen in the industry across all the packaging platforms (WLCSP1, FanOut2, Embedded Die2, Flip Chip3 and 3DIC4). Challenges, applications, positioning of the different packaging technologies by market segments (from low end to high end applications) and changes of the markets and drivers, growth rates and roadmaps will be presented. Global capacities and demands and the landscape of the packaging industry will be reviewed. Examples of teardowns to illustrate the latest packaging techniques for various devices used in latest products will be included.

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