scholarly journals Implementation of LPDDR4 Memory Interface Using AXI3 Protocol with Optimization Technique

2021 ◽  
Vol 23 (06) ◽  
pp. 1313-1317
Author(s):  
Gopalakrishna P ◽  
◽  
Dr. P. A. Vijaya ◽  
Keyword(s):  
Intellectual Property ◽  
Low Power ◽  
Optimization Technique ◽  
System On Chip ◽  
Single Chip ◽  
Chip Design ◽  
Code Coverage ◽  
On Chip ◽  
The Given ◽  
Digital Or

In electronics, one of the complex designs is SOC (system on chip) design, where many of the predefined or IP (intellectual property) circuits which can be analog, digital, or mixed-signal will be combined with each other and said that many circuits are combined to a single chip. In this paper, it is been designed the low power double data rate version of 4 memory (LPDDR4). It is one of the SDRAM architecture and since it is a memory there should be required a protocol to read data from memory and to write data from the memory for that purpose an AXI3 protocol is been used and the memory controller is been used to check the given input from the AXI protocol is correct or not. The entire SOC design is implemented using Verilog code and checked in the Xilinx 14.7 ISE and simulation is verified then the RTL is viewed in ModelSim 10.5 tool and verified the code coverage of design and testbench.

scholarly journals Little Core Based System on Chip Platform for Internet of Thing

2015 ◽  
Vol 5 (4) ◽  
pp. 695 ◽  
Author(s):  
Sang Don Kim ◽  
Seung Eun Lee
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Reduction ◽  
System On Chip ◽  
Single Chip ◽  
Technology Scaling ◽  
Battery Power ◽  
Iot Platform ◽  
On Chip ◽  
Internet Of Thing

Although the technology scaling has enabled designers to integrate a large number of hardware blocks onto a single chip realizing System on Chip (SoC), problems arising from leakage current have made power reduction an important issue. The IoT platform has restricted power consumption because of battery power. In this paper, we propose our little core based IoT platform focusing on the low power and expandability. The experimental results demonstrate the feasibility of our proposal to the IoT.

scholarly journals Contention Mitigation based Level Shifter Architecture

2021 ◽  
Vol 9 (VI) ◽  
pp. 1664-1669
Author(s):  
Shravan M Jakkannavar
Keyword(s):  
Energy Efficiency ◽  
Low Power ◽  
Input Signal ◽  
Current System ◽  
System On Chip ◽  
Operating Conditions ◽  
Chip Design ◽  
Voltage Level ◽  
Level Shifter ◽  
On Chip

Energy efficiency is one of the most important issues that needs to be solved in the current system on chip design. To overcome this issue, many circuits inside the chip run at low power. However there are some blocks like memories that run at relatively higher voltages. This means, modern day SOC contains different voltages running through it. The problem arises when two blocks operating at different voltages want to communicate with each other. This problem is solved by using Level Shifters as an interfacer between the blocks. The function of Level Shifter is to convert voltage level of input signal to that of the output. In this paper a cross coupled architecture of Level Shifter is proposed which operates between 1.5v and 5v. The speciality of this architecture is there is less contention between pull up network and pull down network, which reduces the rise and fall delay significantly. The proposed design is simulated at different operating conditions and the functionality is checked.

Low‐power enhanced system‐on‐chip design for sequential minimal optimisation learning core with tri‐layer bus and butterfly‐path accelerator

2015 ◽  
Vol 9 (2) ◽  
pp. 93-100 ◽  
Author(s):  
Chih‐Hsiang Peng ◽  
Po‐Chuan Lin ◽  
Shovan Barma ◽  
Jhing‐Fa Wang ◽  
Hong‐Yuan Peng ◽  
...  
Keyword(s):  
Low Power ◽  
System On Chip ◽  
Chip Design ◽  
On Chip
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