scholarly journals Reversible Logic gate based on QSD Addition/Subtraction using DPG Gate

2019 ◽  
Vol 182 (47) ◽  
pp. 42-45
Author(s):  
Asiya Hasan ◽  
Nishi Pandey ◽  
Meha Shrivastava
Keyword(s):  
Logic Gate ◽  
Reversible Logic

A target-induced logically reversible logic gate for intelligent and rapid detection of pathogenic bacterial genes

2018 ◽  
Vol 54 (25) ◽  
pp. 3110-3113 ◽  
Author(s):  
Jiankang Deng ◽  
Zhanhui Tao ◽  
Yaqing Liu ◽  
Xiaodong Lin ◽  
Pengcheng Qian ◽  
...  
Keyword(s):  
Output Signal ◽  
Rapid Detection ◽  
Logic Gate ◽  
Reversible Logic ◽  
Feynman Gate ◽  
Bacterial Genes

A target-induced Feynman gate acts as an intelligent biosensor to distinguish all information of the targets from the output signal patterns.

Design of Quantum Cost, Garbage Output and Delay Optimized BCD to Excess-3 and 2’s Complement Code Converter

2018 ◽  
Vol 27 (12) ◽  
pp. 1850184 ◽  
Author(s):  
Heranmoy Maity ◽  
Arijit Kumar Barik ◽  
Arindam Biswas ◽  
Anup Kumar Bhattacharjee ◽  
Anita Pal
Keyword(s):  
Logic Gate ◽  
Logic Circuits ◽  
Reversible Logic ◽  
Combinational Logic ◽  
Quantum Cost ◽  
Code Converter ◽  
Garbage Output ◽  
Combinational Logic Circuits ◽  
Logic Functions

In this paper, we have proposed a new reversible logic gate (NG) and also the quantum cost (QC), garbage outputs, delay optimized reversible combinational logic circuits such as four bit 2’s complement code converter circuit, BCD to Excess-3 code converter using reversible logic gate. The proposed NG is used to design a four bit 2’s complement code converter circuit, BCD to Excess-3 code converter and realization of different logic functions such as NOT, AND, NAND, OR, NOR, XOR, NXOR. The proposed (new reversible logic) gate is represented by quantum implementation. The proposed work is verified by Xilinx-ISE simulator software and others logic circuits are also verified. The QC of proposed gate is 5. The QC of four bit 2’s complement code converter and BCD to Excess-3 code converter are 11 and 14 which are better with respect to previous reported results.

scholarly journals Optimal energy estimation of Toffoli and Peres gate design using quantum-dot cellular automata

2021 ◽  
Author(s):  
Mukesh Patidar ◽  
Namit Gupta
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Logic Gate ◽  
Research Work ◽  
Single Layer ◽  
Reversible Logic ◽  
Effect Of Temperature ◽  
Toffoli Gate ◽  
Energy Estimation ◽  
Quantum Dot Cellular Automata

Abstract Quantum-dot cellular automata (QCA) are a novel dominant transistor-less computational nanotechnology. It is an appropriate candidate for the upcoming generation of quantum computational nano-electronics technology. The main objective of this research work is to present a QCA reversible logic circuits design such as the Toffoli gate (TG) and Peres gate (PG) and do the analysis of different parameters. In this paper, we propose a single layer coplanar method to solve this physical layout design and synchronization problem. The presented reversible logic gate (RLG) layout designs are implemented by Bijection functional algorithm for reduction of the number of QCA (quantum) cells, latency, and minimum design area. Also, the Optimized energy dissipation and effect of temperature on output polarization cell, of the proposed structure have been checked successfully using the tool QD-E (Energy) tool. The proposed QCA design has been verified by QCADesigner-E 2.2 tool using a bistable approximation and coherence vector engine. Finally, comparisons have been proposed RLG-TG and RLG-PG designs with the existing QCA design.

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