scholarly journals Performance Analysis of Dual Core, Core 2 Duo and Core i3 Intel Processor

2015 ◽  
Vol 120 (10) ◽  
pp. 1-7 ◽  
Author(s):  
Taiwo O.Ojeyinka ◽  
Olusola Olajide Ajayi
Keyword(s):  
Performance Analysis ◽  
Dual Core

scholarly journals Enabling Parallelized-QEMU for Hardware/Software Co-Simulation Virtual Platforms

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 759
Author(s):  
Edel Díaz ◽  
Raúl Mateos ◽  
Emilio J. Bueno ◽  
Rubén Nieto
Keyword(s):  
Performance Analysis ◽  
Industrial Application ◽  
The Novel ◽  
San Jose ◽  
Synchronization Mechanism ◽  
Grid Monitoring ◽  
Parallel Mode ◽  
Software And Hardware ◽  
Software Emulator ◽  
Dual Core

Presently, the trend is to increase the number of cores per chip. This growth is appreciated in Multi-Processor System-On-Chips (MPSoC), composed of more cores in heterogeneous and homogeneous architectures in recent years. Thus, the difficulty of verification of this type of system has been great. The hardware/software co-simulation Virtual Platforms (VP) are presented as a perfect solution to address this complexity, allowing verification by simulation/emulation of software and hardware in the same environment. Some works parallelized the software emulator to reduce the verification times. An example of this parallelization is the QEMU (Quick EMUlator) tool. However, there is no solution to synchronize QEMU with the hardware simulator in this new parallel mode. This work analyzes the current software emulators and presents a new method to allow an external synchronization of QEMU in its parallelized mode. Timing details of the cores are taken into account. In addition, performance analysis of the software emulator with the new synchronization mechanism is presented, using: (1) a boot Linux for MPSoC Zynq-7000 (dual-core ARM Cortex-A9) (Xilinx, San Jose, CA, USA); (2) an FPGA-Linux co-simulation of a power grid monitoring system that is subsequently implemented in an industrial application. The results show that the novel synchronization mechanism does not add any appreciable computational load and enables parallelized-QEMU in hardware/software co-simulation virtual platforms.

Performance analysis of the GR712RC dual-core LEON3FT SPARC V8 processor in an asymmetric multi-processing environment

2016 ◽  
Author(s):  
Giovanni Giusi ◽  
Scige J. Liu ◽  
Emanuele Galli ◽  
Anna M. Di Giorgio ◽  
Maria Farina ◽  
...  
Keyword(s):  
Performance Analysis ◽  
Dual Core

scholarly journals Performance analysis of a modal converter based on an asymmetric dual-core photonic crystal fiber

2017 ◽  
Vol 50 (3) ◽  
pp. 251-257 ◽  
Author(s):  
E. Reyes-Vera ◽  
J. Úsuga ◽  
J. Acevedo-Echeverry ◽  
N. Gómez-Cardona ◽  
M. Varón
Keyword(s):  
Photonic Crystal ◽  
Performance Analysis ◽  
Photonic Crystal Fiber ◽  
Crystal Fiber ◽  
Dual Core

scholarly journals Fostering Analysis from Industrial Embedded Systems Modeling

2014 ◽  
pp. 283-300 ◽  
Author(s):  
Michel Bourdellès ◽  
Shuai Li ◽  
Imran Quadri ◽  
Etienne Brosse ◽  
Andrey Sadovykh ◽  
...  
Keyword(s):  
Performance Analysis ◽  
Embedded Systems ◽  
Development Process ◽  
System Development ◽  
System Modeling ◽  
Systems Development ◽  
Development Projects ◽  
Early Stages ◽  
Dual Core

In most industrial embedded systems development projects, the software and the hardware development parts are separated, and the constraint requirements/capabilities are informally exchanged in the system development phase of the process. To prevent failures due to the violation of timing constraints, hardware components of the platform are typically over dimensioned for the capabilities needed. This increases both cost and power consumption. Performance analysis is not done sufficiently at early stages of the development process to optimize the system. This chapter presents results of the integration of tools and extra modeling to offer new performance analysis capabilities in the early stages of the development process. These results are based on trace generation from code instrumentation. A number of enhancements were made, spanning the system modeling stage down to the execution stage (based on an ARM dual core Cortex A9-based target board). Final results taken from a software-based radio case study (including the analysis and validation stages) are presented.

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