scholarly journals Automatic SystemC Code Generation from UML Models at Early Stages of Systems on Chip Design

2010 ◽  
Vol 8 (6) ◽  
pp. 10-17 ◽  
Author(s):  
Fateh Boutekkouk
Keyword(s):  
Code Generation ◽  
Chip Design ◽  
Early Stages ◽  
Systems On Chip ◽  
On Chip ◽  
Uml Models

3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

2001 ◽  
Vol 89 (5) ◽  
pp. 602-633 ◽  
Author(s):  
K. Banerjee ◽  
S.J. Souri ◽  
P. Kapur ◽  
K.C. Saraswat
Keyword(s):  
Chip Design ◽  
Systems On Chip ◽  
Deep Submicrometer ◽  
On Chip

Special Issue on Systems-on-Chip: Design and Integration

2006 ◽  
Vol 94 (6) ◽  
pp. 1045-1049
Author(s):  
Graham Jullien ◽  
Magdy Bayoumi
Keyword(s):  
Special Issue ◽  
Chip Design ◽  
Systems On Chip ◽  
On Chip

SOC DESIGN FOR WIRELESS COMMUNICATIONS

2011 ◽  
Vol 20 (08) ◽  
pp. 1505-1527 ◽  
Author(s):  
ZORAN STAMENKOVIĆ
Keyword(s):  
Error Detection ◽  
High Performance ◽  
Basic Knowledge ◽  
Embedded Devices ◽  
Chip Design ◽  
Wireless Applications ◽  
Systems On Chip ◽  
Early Error ◽  
Custom Hardware ◽  
On Chip

The paper emphasizes methods, architectures, and components for system-on-chip design. It describes the basic knowledge and skills for designing high-performance low-power embedded devices whose complexity increases exponentially, as so does the effort of designing them. Relying upon an appropriate design methodology which concentrates on reuse, executable specifications, and early error detection, these complexities can be mastered. The paper bundles these topics in order to provide a good understanding of all the problems involved. It shows how to go from description and verification to implementation and testing, presenting three systems-on-chip for three different wireless applications based on configurable processors and custom hardware accelerators.

A Classification and Evaluation Framework for NoC Mapping Strategies

2016 ◽  
Vol 26 (02) ◽  
pp. 1730001 ◽  
Author(s):  
Toubaline Nesrine ◽  
Bennouar Djamel ◽  
Mahdoum Ali
Keyword(s):  
Network On Chip ◽  
Evaluation Framework ◽  
Challenging Problem ◽  
Chip Design ◽  
Networks On Chip ◽  
Systems On Chip ◽  
Target Architecture ◽  
On Chip ◽  
The Moment ◽  
The Impact

Network on Chip (NoC) is a new communication medium used for systems-on-chip (SoCs). In an SoC, the placement of the communicating elements across the network has an impact on system performance. Such a placing is called the MAPPING phase in networks on chip design process. Many approaches dealing with the mapping phase have been proposed but selecting the best technique for a given NoC remains a challenging problem. This paper attempts to provide an answer to this issue. It motivates and presents a definition and a classification according to some criteria: (i) the algorithms used for solving the mapping problem, (ii) the moment in which the mapping is executed, (iii) the impact of combining mapping with other phases during NoC design and (iv) the target architecture.

Network-on-Chip Design for Gigascale Systems-on-Chip

2005 ◽  
pp. 21-1-21-19
Author(s):  
Luca Benini ◽  
Davide Bertozzi ◽  
Giovanni De Micheli
Keyword(s):  
Network On Chip ◽  
Chip Design ◽  
Systems On Chip ◽  
On Chip

scholarly journals Towards an Ontology-driven Intellectual Properties reuse for Systems On Chip design

2021 ◽  
Vol 15 ◽  
pp. 78-83
Author(s):  
Fateh Boutekkouk
Keyword(s):  
System On Chip ◽  
Levels Of Abstraction ◽  
Chip Design ◽  
Time To Market ◽  
Standard Representation ◽  
Design Language ◽  
Systems On Chip ◽  
Widespread Acceptance ◽  
On Chip ◽  
Intellectual Properties

Intellectual Properties reuse has gained widespread acceptance in System-On-Chip design to manage the complexity and shorten the time-to-market. However the need for a standard representation that permits IPs classification, characterization, and integration is still a big challenge. To address this problem, we propose to develop an IPs reuse specific ontology that facilitates IPs reuse at many levels of abstraction and independently from any design language or tool. Our ontology is built using the Protégé-OWL tool

Effective Memory Architectures of Multi-Processor Systems-on-Chip

2010 ◽  
Vol 3 (3) ◽  
pp. 218-231
Author(s):  
Ni Zhou ◽  
Fei Qiao ◽  
Huazhong Yang ◽  
Hui Wang
Keyword(s):  
Systems On Chip ◽  
On Chip ◽  
Memory Architectures
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