scholarly journals IMPLEMENTATION OF ROBUST ARCHITECTURE FOR ERROR DETECTION AND DATA RECOVERY IN MOTION ESTIMATION ON FPGA

2013 ◽  
pp. 29-33
Author(s):  
V.V.. S.V.S RAMACHANDRAM ◽  
DANIEL N. FINNEY
Keyword(s):  
Motion Estimation ◽  
Video Coding ◽  
Video Compression ◽  
Error Detection ◽  
Video Data ◽  
Data Recovery ◽  
Concurrent Error Detection ◽  
Coding Systems ◽  
Wide Range ◽  
Total Data

Video compression is necessary in a wide range of applications to reduce the total data amount required for transmitting or storing video data. Among the coding systems, Motion Estimation is of priority concern in exploiting the temporal redundancy between successive frames, yet also the most time consuming aspect of coding. This paper presents an error detection and data recovery (EDDR) design, based on the residue-and quotient (RQ) code that is embed into ME for video coding testing applications. Based on the Concurrent Error Detection (CED) concept, this work develops a robust EDDR architecture based on the RQ code to detect errors and recovery data in PEs of a ME and, in doing so, further guarantee the excellent reliability for video coding applications. We synthesized this design using Xilinx tool.

scholarly journals DESIGN FOR TESTABILITY TECHNIQUES FOR VIDEO CODING SYSTEMS

2013 ◽  
pp. 276-281
Author(s):  
PARSHA SRIKANTH ◽  
SD.RAZIYA SULTHANA
Keyword(s):  
Motion Estimation ◽  
Video Coding ◽  
Error Detection ◽  
High Reliability ◽  
Data Recovery ◽  
Experimental Result ◽  
Coding System ◽  
Processing Elements ◽  
Estimation Algorithms ◽  
Coding Systems

Motion estimation algorithms are used in various video coding systems. While focusing on the testing of ME in a video coding system, this work presents an error detection and data recovery (EDDR) design, based on the residue-andquotient (RQ) code, to embed into ME for video coding testing applications. An error in processing elements (PEs), i.e. key components of a ME, can be detected and recovered effectively by using the proposed EDDR design. Therefore, paper describes a novel testing scheme of motion estimation. The key part of this scheme is to offer high reliability for motion estimation architecture. The experimental result shows the design achieve 100% fault coverage. And, the main advantages of this scheme are minimal performance degradation, small cost of hardware overhead and the benefit of at speed testing.

scholarly journals DESIGN OF AN ERROR DETECTION AND DATA RECOVERY ARCHITECTURE FOR MOTION ESTIMATION TESTING APPLICATIONS

2014 ◽  
pp. 225-229
Author(s):  
V. SWARNALATHA ◽  
K. SRINIVASA RAO
Keyword(s):  
Motion Estimation ◽  
Video Coding ◽  
Error Detection ◽  
Critical Role ◽  
Data Recovery ◽  
Coding System ◽  
Processing Elements

Motion estimation (ME) in a video coding system is the critical role, so testing such a module is of priority concern. While focusing on the testing of ME in a video coding system, this work presents an error detection and data recovery (EDDR) design based on residue -and- quotient (RQ) code. An error in processing elements (PEs) can be detected and recovered effectively by using the proposed EDDR design. Importantly, the proposed EDDR design performs satisfactorily in terms of throughput and reliability for motion estimation (ME) testing applications.

scholarly journals Review on Architectures of Motion Estimation for Video Coding Standards

2018 ◽  
Vol 7 (4.10) ◽  
pp. 928
Author(s):  
Prayline Rajabai C ◽  
Sivanantham S
Keyword(s):  
Motion Estimation ◽  
Video Coding ◽  
Video Compression ◽  
Video Data ◽  
Video Codec ◽  
Current Frame ◽  
Estimation Algorithms ◽  
Hardware Architectures ◽  
Coding Standards ◽  
Extensive Computation

Various video coding standards like H.264 and H.265 are used for video compression and decompression. These coding standards use multiple modules to perform video compression. Motion Estimation (ME) is one of the critical blocks in the video codec which requires extensive computation. Hence it is computationally complex, it critically consumes a massive amount of time to process the video data. Motion Estimation is the process which improves the compression efficiency of these coding standards by determining the minimum distortion between the current frame and the reference frame. For the past two decades, various Motion Estimation algorithms are implemented in hardware and research is still going on for realizing an optimized hardware solution for this critical module. Efficient implementation of ME in hardware is essential for high-resolution video applications such as HDTV to increase the decoding throughput and to achieve high compression ratio. A review and analysis of various hardware architectures of ME used for H.264 and H.265 coding standards is presented in this paper.  

scholarly journals Scalable FPGA Hardware Acceleration for H.264 Motion Estimation

2021 ◽  
Author(s):  
Theepan Moorthy
Keyword(s):  
Motion Estimation ◽  
Real Time ◽  
Video Compression ◽  
Reference Frames ◽  
Hardware Acceleration ◽  
Compressed Video ◽  
Time Performance ◽  
Wide Range ◽  
Multiple Reference Frames ◽  
Multiple Reference

The H.264 video compression standard uses enhanced Motion Estimation (ME) features to improve both the compression ratio and the quality of compressed video. The two primary enhancements are the use of Variable Block Size Motion Estimation (VBSME) and multiple reference frames. These two additions greatly increase the computational complexity of the ME algorithm, to the point where a software based real-time (30 frames per second (fps)) implementation is not possible on present microprocessors. Thus hardware acceleration of the H.264 ME algorithm is necessary in order to achieve real-time performance for the implementation of the VBSME and multiple reference frames features. This thesis presents a scalable FPGA-based ME architecture that supports real-time H.264 ME for a wide range of video resolutions ─ from 640x480 VGA to 1920x1088 High Definition (HD). The architecture contains innovations in both the data-path design and memory organization to achieve scalability and real-time performance on FPGAs. At 37% FPGA device utilization, the architecture is able to achieve 31 fps performance for encoding full 1920x1088 progressive HDTV video.

Block-Based Motion Estimation

2021 ◽  
pp. 651-676
Author(s):  
Shaifali Madan Arora ◽  
Kavita Khanna
Keyword(s):  
Video Coding ◽  
Resource Utilization ◽  
Video Compression ◽  
Visual Information ◽  
Video Data ◽  
Technological Evolution ◽  
High Bandwidth ◽  
Block Based ◽  
The Cost ◽  
And Storage

Recent years have witnessed a great technological evolution in video display and capturing technologies leading to the development of new standards of video coding including MPEG-X, H.26X and HEVC. The cost of computations, storage and high bandwidth requirements makes a video data expensive in terms of transmission and storage. This makes video compression absolutely necessary prior to its transmission in order to accommodate for different transmission media's capabilities. Digital video compression technologies therefore have become an important part of the way we create, present, communicate and use visual information. The main aim behind a video compression system is to eliminate the redundancies from a raw video signal. The tradeoff involved in the process of video compression is between the speed, quality and resource utilization. The current chapter explores the techniques, challenges, issues and problems in video compression in detail along with the major advancements in the field.

scholarly journals Scalable FPGA Hardware Acceleration for H.264 Motion Estimation

2021 ◽  
Author(s):  
Theepan Moorthy
Keyword(s):  
Motion Estimation ◽  
Real Time ◽  
Video Compression ◽  
Reference Frames ◽  
Hardware Acceleration ◽  
Compressed Video ◽  
Time Performance ◽  
Wide Range ◽  
Multiple Reference Frames ◽  
Multiple Reference

The H.264 video compression standard uses enhanced Motion Estimation (ME) features to improve both the compression ratio and the quality of compressed video. The two primary enhancements are the use of Variable Block Size Motion Estimation (VBSME) and multiple reference frames. These two additions greatly increase the computational complexity of the ME algorithm, to the point where a software based real-time (30 frames per second (fps)) implementation is not possible on present microprocessors. Thus hardware acceleration of the H.264 ME algorithm is necessary in order to achieve real-time performance for the implementation of the VBSME and multiple reference frames features. This thesis presents a scalable FPGA-based ME architecture that supports real-time H.264 ME for a wide range of video resolutions ─ from 640x480 VGA to 1920x1088 High Definition (HD). The architecture contains innovations in both the data-path design and memory organization to achieve scalability and real-time performance on FPGAs. At 37% FPGA device utilization, the architecture is able to achieve 31 fps performance for encoding full 1920x1088 progressive HDTV video.

scholarly journals Efficient and Low Complexity Surveillance Video Compression using Distributed Scalable Video Coding

2018 ◽  
Vol 34 (1) ◽  
Author(s):  
Le Dao Thi Hue ◽  
Luong Pham Van ◽  
Duong Dinh Trieu ◽  
Xiem HoangVan
Keyword(s):  
Video Coding ◽  
Video Compression ◽  
Video Surveillance ◽  
High Efficiency ◽  
Scalable Video Coding ◽  
Low Complexity ◽  
Video Data ◽  
Base Layer ◽  
Scalable Video ◽  
Surveillance Video

Video surveillance has been playing an important role in public safety and privacy protection in recent years thanks to its capability of providing the activity monitoring and content analyzing. However, the data associated with long hours surveillance video is huge, making it less attractive to practical applications. In this paper, we propose a low complexity, yet efficient scalable video coding solution for video surveillance system. The proposed surveillance video compression scheme is able to provide the quality scalability feature by following a layered coding structure that consists of one or several enhancement layers on the top of a base layer. In addition, to maintain the backward compatibility with the current video coding standards, the state-of-the-art video coding standard, i.e., High Efficiency Video Coding (HEVC), is employed in the proposed coding solution to compress the base layer. To satisfy the low complexity requirement of the encoder for the video surveillance systems, the distributed coding concept is employed at the enhancement layers. Experiments conducted for a rich set of surveillance video data shown that the proposed surveillance - distributed scalable video coding (S-DSVC) solution significantly outperforms relevant video coding benchmarks, notably the SHVC standard and the HEVC-simulcasting while requiring much lower computational complexity at the encoder which is essential for practical video surveillance applications.

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