scholarly journals Design & Implementation of Low Power 3-bit Flash ADC in 0.18μm CMOS

2012 ◽  
pp. 89-93
Author(s):  
Pradeep Kumar ◽  
Amit Kolhe
Keyword(s):  
Power Consumption ◽  
Response Time ◽  
Low Power ◽  
Cmos Technology ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Chip Area ◽  
Flash Adc ◽  
Analog To Digital ◽  
Design And Implementation

This paper describes the design and implementation of a Low Power 3-bit flash Analog to Digital converter (ADC). It includes 7 comparators and one thermometer to binary encoder. It is implemented in 0.18um CMOS Technology. The presimulation of ADC is done in T-Spice and post layout simulation is done in Microwind3.1. The response time of the comparator equal to 6.82ns and for Flash ADC as 18.77ns.The Simulated result shoes the power consumption in Flash ADC as is 36.273mw .The chip area is for Flash ADC is 1044um2 .

A Low-Power Low-Distortion 20-GS/s Flash Analog-to-Digital Converter for Coherent Optical Receiver in 0.13-μm SiGe BiCMOS

2019 ◽  
Vol 28 (10) ◽  
pp. 1950167 ◽  
Author(s):  
Jiquan Li ◽  
Yingmei Chen ◽  
Pan Tang ◽  
Zhen Zhang ◽  
Hui Wang ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Optical Receiver ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Flash Adc ◽  
Analog To Digital ◽  
Offset Voltage ◽  
Bicmos Technology ◽  
Sige Bicmos

High-speed, low-power analog-to-digital converter (ADC) is a critical element for 5-GBd, 20-Gb/s digital signal processing (DSP)-based coherent optical communication receiver. To satisfy high data transmission rate requirement of optical receiver, a single-core and open-loop flash ADC with a new proposed multiplexer-based encoder is presented in this paper. Compared with conventional encoder topology, the new proposed topology achieves the fastest encoding speed and lowest power consumption. The optimized distortion is achieved by utilizing a leakage current compensation technique and a local negative feedback method in switched-buffer track-and-hold amplifier (THA). Strict synchronization is obtained for clock signals by careful designing of layout in tree-based clock networks. Furthermore, a master–slave comparator incorporated with a preamplifier reduces signal-dependent kickback noise as well as offset voltage. By using master–slave comparators and proposed encoders, the sampling rate is up to 21.12[Formula: see text]GS/s. The 4-bit, 20-GS/s flash ADC is realized in 0.13-[Formula: see text]m SiGe BiCMOS technology and it only occupies 1.05[Formula: see text]mm[Formula: see text][Formula: see text][Formula: see text]1.46[Formula: see text]mm chip area. With a power consumption of 1.831[Formula: see text]W from 4-V supply, the ADC achieves an effective number of bits (ENOB) of 2.5 at 15[Formula: see text]GS/s.

scholarly journals A 1000 Mhz Low Power and High Speed 8-Bit Flash ADC Architecture using 90nm Cmos Technology

2019 ◽  
Vol 8 (11S) ◽  
pp. 11-19
Keyword(s):  
Comparative Analysis ◽  
High Resolution ◽  
Low Power ◽  
Time Domain ◽  
High Speed ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Digital Converter ◽  
Flash Adc ◽  
Analog To Digital

The design objective is to implement a Low power, High speed and High resolution Flash ADC with increased sampling rate. To make this possible the blocks of ADC are analyzed. The resistive ladder, comparator block, encoder block are the major modules of flash ADC. Firstly, the comparator block is designed so that it consumes low power. A NMOS latch based, PMOS LATCH based and a Strong ARM Latch based comparators were designed separately. A comparative analysis is made with the comparator designs. Comparators in the design is reduced to half by using time domain interpolation. Then a reference subtraction block is designed to generate the subtraction value of voltages easily and its given as input to comparator. Then a more efficient and low power consuming fat tree encoder is designed. Once all the blocks were ready, a 8 bit Flash Analog to Digital Converter was designed using 90nm CMOS technology and all the parameters such as sampling rate, power consumption, resolution were obtained and compared with other works.

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