scholarly journals COUNTING BLOOM FILTER ARCHITECTURE IN VLSI NETWORK SYSTEMS

Author(s):  
NAGAMALLI. A ◽  
KEDARESWARARAO. M

The Counting Bloom Filter (CBF) is useful for real time applications where the time and space efficiency is the main consideration in performing a set membership tests. The CBF estimates whether an element is present in a large array or not by allowing false positives and by not permitting false negatives. In this paper CBF architecture is analyzed and has been implemented. There are two approaches of CBF, SRAM based approach using up/down counters and the LCBF using up/down LFSR unit. In this paper the LCBF architecture discussed and analyzed. In the latest VLSI technology it is easy to fabricate memories that hold a few million bits of data and addresses. But in the recent embedded memory technologies rather than mapping of addresses of 5000 bits of data using hashing functions we can concise in to single contiguous memory.

2014 ◽  
Vol 22 (4) ◽  
pp. 1092-1105 ◽  
Author(s):  
Ori Rottenstreich ◽  
Yossi Kanizo ◽  
Isaac Keslassy

2016 ◽  
Vol 116 (4) ◽  
pp. 304-309 ◽  
Author(s):  
Salvatore Pontarelli ◽  
Pedro Reviriego ◽  
Juan Antonio Maestro

2013 ◽  
Vol 427-429 ◽  
pp. 2554-2557
Author(s):  
Jin Kun Pan ◽  
Dong Sheng Li

With the popularity of location-based services, Web contents are being geo-tagged and spatial keyword queries that retrieve objects satisfying both spatial and keyword conditions are gaining in prevalence. The existing spatial keyword queries focus on exact match or prefix match of the keywords cannot satisfy the demand of wildcard based imprecise match in many realistic scenes. Aiming to solve this problem, two methods which are fit for different situation are put forward: the inverted file and R-tree integrated index which fits for the situation that requires high time efficiency and the Prefix Bloom Filter and R-tree integrated index which fits for the situation requiring high space efficiency. The effectiveness of the two indexes is valid through experiments.


Author(s):  
Zhou Mingzhong ◽  
Gong Jian ◽  
Ding Wei ◽  
Cheng Guang

2019 ◽  
Vol 9 (2) ◽  
pp. 329 ◽  
Author(s):  
Hayoung Byun ◽  
Hyesook Lim

Network traffic has increased rapidly in recent years, mainly associated with the massive growth of various applications on mobile devices. Named data networking (NDN) technology has been proposed as a future Internet architecture for effectively handling this ever-increasing network traffic. In order to realize the NDN, high-speed lookup algorithms for a forwarding information base (FIB) are crucial. This paper proposes a level-priority trie (LPT) and a 2-phase Bloom filter architecture implementing the LPT. The proposed Bloom filters are sufficiently small to be implemented with on-chip memories (less than 3 MB) for FIB tables with up to 100,000 name prefixes. Hence, the proposed structure enables high-speed FIB lookup. The performance evaluation result shows that FIB lookups for more than 99.99% of inputs are achieved without needing to access the database stored in an off-chip memory.


2019 ◽  
Vol 28 (12) ◽  
pp. 1950203
Author(s):  
Sajjad Rostami-Sani ◽  
Mojtaba Valinataj ◽  
Saeideh Alinezhad Chamazcoti

The cache system dissipates a significant amount of energy compared to the other memory components. This will be intensified if a cache is designed with a set-associative structure to improve the system performance because the parallel accesses to the entries of a set for tag comparisons lead to even more energy consumption. In this paper, a novel method is proposed as a combination of a counting Bloom filter and partial tags to mitigate the energy consumption of set-associative caches. This new hybrid method noticeably decreases the cache energy consumption especially in highly-associative instruction caches. In fact, it uses an enhanced counting Bloom filter to predict cache misses with a high accuracy as well as partial tags to decrease the overall cache size. This way, unnecessary tag comparisons can be prevented and therefore, the cache energy consumption is considerably reduced. Based on the simulation results, the proposed method provides the energy reduction from 22% to 31% for 4-way–32-way set-associative L1 caches bigger than 16[Formula: see text]kB running the MiBench programs. The improvements are attained with a negligible system performance degradation compared to the traditional cache system.


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