Design and Verification of SDRAM Controller Based on FPGA

The implementation of a camera system with a field programmable gate array (FPGA) is an important step within research towards constructing a video processing architecture design based on FPGA. This paper presents the design and implementation of a camera system using the Nios II soft-core embedded processor from Altera. The proposed camera system is a flexible platform for the implementation of other systems such as image processing and video processing. The system architecture is designed using the Quartus II SOPC Builder System and implemented on an Altera DE2-70 development platform. The image or video is captured using a Terasic TRDB-D5M camera and stored into two different synchronous dynamic random access memories (SDRAM) using an SDRAM Controller. The specifications of the Terasic TRDB-D5M and SDRAM are examined to confirm that the recorded and stored data match. The results of this experiment show that the system is able to record and store data correctly into SDRAM. The data in the SDRAM correctly displays the recorded image on a VGA monitor.

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SDRAM Controller for Retention Time Analysis in Low Power Signal Processor

Lecture Notes in Electrical Engineering - Proceedings of the Fourth International Conference on Signal and Image Processing 2012 (ICSIP 2012) ◽

10.1007/978-81-322-1000-9_29 ◽

2013 ◽

pp. 303-309

Author(s):

Sang Don Kim ◽

Yeong Seob Jeong ◽

Ju Seong Lee ◽

Seung Eun Lee

Keyword(s):

Low Power ◽

Retention Time ◽

Time Analysis ◽

Sdram Controller ◽

Signal Processor

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An FPGA based SDRAM controller with complex QoS scheduling and traffic shaping (abstract only)

Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays - FPGA '05 ◽

10.1145/1046192.1046260 ◽

2005 ◽

Author(s):

Sven Heithecker ◽

Rolf Ernst

Keyword(s):

Traffic Shaping ◽

Sdram Controller

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A Customizable DDR3 SDRAM Controller Tailored for FPGA-Based Data Buffering Inside Real-Time Range-Doppler Radar Signal Processing Back Ends

IEEE EUROCON 2019 -18th International Conference on Smart Technologies ◽

10.1109/eurocon.2019.8861603 ◽

2019 ◽

Author(s):

Vladimir M. Milovanovic ◽

Darko M. Tasovac

Keyword(s):

Signal Processing ◽

Real Time ◽

Doppler Radar ◽

Radar Signal ◽

Time Range ◽

Radar Signal Processing ◽

Sdram Controller

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An Application on Controller to Improve Performance of Multi-Core Shared Memory Based on Network Processing

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.403-408.2107 ◽

2011 ◽

Vol 403-408 ◽

pp. 2107-2110

Author(s):

Pei Jun Ma ◽

Yu Jia Peng ◽

Kang Li ◽

Jiang Yi Shi ◽

Qing Guang

Keyword(s):

Shared Memory ◽

Control Logic ◽

Improve Performance ◽

Sdram Controller ◽

Network Processing

An application to improve the performance of Multi-Core shared memory based on network processing is described in this paper. In order to get more instructions with address relevancy, the function of chain is applied on the design of SDRAM controller. The application of chain needs to rely on the design of arbitration and command control logic. Firstly, the algorithm of the arbitration is adapted to ensure the function of chain bit. Secondly the command control logic is also optimized to support addressing SDRAM memory efficiently. The verified results show that the efficiency of the SDRAM memory can be improved nearly 47.4% after exploiting more instructions with address relevancy.

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