Performance evaluation of massively parallel communication sessions

2019 ◽  
Author(s):  
Z. Gál ◽  
I. Varga ◽  
T. Tajti ◽  
G. Kocsis ◽  
Z. Langmajer ◽  
...  
Keyword(s):  
Performance Evaluation ◽  
Massively Parallel ◽  
Parallel Communication

Performance Evaluation of a Massively Parallel Decoder for CISC Microprocessors

2011 ◽  
Vol 65 ◽  
pp. 590-594
Author(s):  
Jian Feng An ◽  
Xiao Ya Fan ◽  
Jun Zhang ◽  
Hai Feng Yi
Keyword(s):  
Performance Evaluation ◽  
Massively Parallel ◽  
Simulation Results

Performance of the decoder unit is critical for CISC microprocessors. To take x86 ISA for an example, we analyzes the x86 instruction formats in detail. We compare two decoding strategies used in Longteng C1&C2 microprocessors: One is a simply direct serial decoder; another is a massively parallel decoder. Simulation results show speedups around 2.2~3.6 are obtained by using 10 parallel sub-decoders.

Performance evaluation of a massively parallel I/O subsystem

1994 ◽  
Vol 22 (4) ◽  
pp. 5-10 ◽  
Author(s):  
Sandra Johnson Baylor ◽  
Caroline Benveniste ◽  
Yarsun Hsu
Keyword(s):  
Performance Evaluation ◽  
Massively Parallel

Routing techniques for massively parallel communication

1991 ◽  
Vol 79 (4) ◽  
pp. 488-503 ◽  
Author(s):  
S.A. Felperin ◽  
L. Gravano ◽  
G.D. Pifarre ◽  
J.L.C. Sanz
Keyword(s):  
Massively Parallel ◽  
Routing Techniques ◽  
Parallel Communication
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