Testing Performance of Application Containers in the Cloud with HPC Loads

2017 ◽  
Author(s):  
N. Muhtaroglu ◽  
B. Kolcu ◽  
I. Ari
Keyword(s):  
Testing Performance

Effects of LD and ADHD on Computerized Neurocognitive Concussion Testing Performance

2013 ◽  
Author(s):  
R. J. Elbin ◽  
Anthony P. Kontos ◽  
Nathan Kegel ◽  
Eric Johnson ◽  
Scott Burkhart ◽  
...  
Keyword(s):  
Testing Performance

scholarly journals Optimization of Scheduling Technique Rooted on Software Test Routines for Embedded Cores using Quality Factor

2020 ◽  
Vol 9 (3) ◽  
pp. 2034-2038
Keyword(s):  
Quality Factor ◽  
Digital Circuits ◽  
Research Work ◽  
Software Test ◽  
Q Factor ◽  
Embedded Cores ◽  
Testing Performance ◽  
Self Test ◽  
Scheduling Technique ◽  
Additional Area

Most of the research work to test the fast processors is carried out using external devices as testers;but it was not technically & financially workable. To fulfill the required performance along with providing efficient functionality, an appropriate testingism must be employed by the digital circuits. The best way is to follow testing as an integral part that is self-test. Conventionally large amount of data was stored in an external tester.But there was a difficulty in at speed testing performance using these external hardware. Hence, Builtin-self-test was invented which verifies failure free nature of circuit under test (CUT) with a test mechanism as a part of system itself. It is observed that, if testing of any hardware is carried out with the help of built-in self test, it increases the requirement of additional area and indirectly responsible for forfeits due to degradation in performance.. If a powerful and power optimized core is to be designed, hardware BIST cannot be afforded due to these limitations. To overcome these disadvantages, a new software based BIST techniques is introduced which relies on software test patterns. Here this paper focuses on rooting of software test routines which works using optimization of scheduling and also a Q- factor is proposed to evaluate the nature of proposed method.

scholarly journals Evaluating Earwitness Identification Procedures: The Effect of Pre-Parade Instructions

2020 ◽  
Author(s):  
Harriet M J Smith ◽  
JENS ROESER ◽  
Nikolas Pautz ◽  
Josh P Davis ◽  
Jeremy Robson ◽  
...  
Keyword(s):  
Cognitive Processes ◽  
False Alarms ◽  
Wrongful Conviction ◽  
Voice Identification ◽  
Sequential Procedures ◽  
Testing Performance ◽  
Low Performance ◽  
Shed Light ◽  
Present Standard ◽  
Identification Procedures

Voice identification parades can be unreliable, as earwitness responses are error-prone. Here we vary pre-parade instructions, testing performance across serial and sequential procedures to examine ways of reducing errors. The participants listened to a target voice and later attempted to identify it from a parade. They were either warned that the target may or may not be present (standard warning), or encouraged to consider responding ‘not present’ because of the associated risk of a wrongful conviction (strong warning). Overall accuracy was low. Performance varied according to instructions and procedure. False alarms were lower on target-absent serial parades following the strong compared to the standard warning. However, the strong warning was associated with higher false alarms on target-absent sequential parades. We discuss the cognitive processes that might drive this effect. Our novel analyses shed light on these results, highlighting the challenges of directly comparing procedures, and revealing position-related effects.

Sign in / Sign up

Export Citation Format

Share Document