Extreme Power Considerations for High Performance Computing

2014 ◽  
Vol 2014 (1) ◽  
pp. 000769-000775
Author(s):  
How Lin
Keyword(s):  
Power Loss ◽  
High Performance ◽  
Dynamic Test ◽  
Path Loss ◽  
Power Delivery ◽  
Thermal Dynamics ◽  
Modeling Methodology ◽  
Power Delivery Network ◽  
Higher Power ◽  
Loss Efficiency

Power demand in the high end computing and data server segments are driving higher power delivery requirements at all packaging levels in a typical system. At the compute device level, compute node cards are now requiring core power supplies with current levels well above 100 amps at 1 volt or less. This imposes severe power delivery challenges in both power supply power conversion efficiency improvement and power delivery path loss minimization. Due to substantial aggregate I2R losses introduced by the current carrying structures in the power delivery paths, depending on the current level used, up to 10% and more of power loss could result. The focus of this paper is in the discussion of novel interconnect structures developed for reduction of current delivery path power loss. i3Electronics Research & Development addresses these extremes with packaging constructs capable of efficient handling in excess of 200 amps at the device level. Through the course of this study, methods were developed for thermal and electrical modeling, dynamic test apparatus and testing. Several test vehicles were built based on concepts with promising modeled results. Power loss / efficiency, thermal dynamics and electrical dynamics were measured using these test vehicles. The measured and modeled results were compared and studied to assess the accuracy of the power delivery network modeling methodology. This paper will present the methods and constructs developed along with the models and test results.

3D Integrated Packaging Approach for High Performance Processor-Memory Module

2013 ◽  
Vol 2013 (1) ◽  
pp. 000452-000457 ◽  
Author(s):  
S. C. Polzer ◽  
W. L. Wilkins ◽  
J. L. Fasig ◽  
M. J. Degerstrom ◽  
B. K. Gilbert ◽  
...  
Keyword(s):  
Thermal Management ◽  
High Performance ◽  
Mechanical Design ◽  
Power Delivery ◽  
Memory Module ◽  
Thermal Test ◽  
Power Delivery Network ◽  
3D Packaging ◽  
Test Chips ◽  
Delivery Network

As high performance computing (HPC) system performance requirements increase, it is necessary to investigate new methods for integrating system components. Of interest is the applicability of 3D packaging approaches to HPC systems. Using thermal test chips, we designed and assembled a 3D processor-memory module with an integrated power delivery network to investigate interconnect density, integration, testability, and rework issues with 3D integrated packaging in an HPC environment. The design was based on interconnection and power delivery requirements for a processor-memory module capable of supporting 64 full-duplex 30G SerDes, routing for 800 processor-to-memory pins, an integrated multi-tiered power delivery network, and a thermal management solution capable of dissipating a nominal processor heat flux of 100 W/cm2. The technologies selected—semi-rigid flex, power connectors, land grid array (LGA) attach with an anisotropic film, and cold plate-based cooling—are all commercially available technologies, which we adapted for this HPC module. As more advanced 3D packaging and integrated circuits become available, these assemblies and components can be incorporated into our approach to increase integration and performance. This design approach also accommodates substitution of thermal test chips in place of functional components, allowing validation of thermal management solutions ahead of the final module design. We will present the electrical-to-mechanical design strategy used to build this module and results of the thermal and electrical analyses, and point to several areas where further development work would be beneficial in the areas of interconnect, power delivery, and mechanical design.

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