Mechanical Stress Analysis and Evaluation of Hybrid Land Grid Array Attached Large Form Factor Organic Modules

2012 ◽  
Vol 2012 (1) ◽  
pp. 000818-000824
Author(s):  
John Torok ◽  
Shawn Canfield ◽  
Yuet-Ying Yu ◽  
Jiantao Zheng
Keyword(s):  
Form Factor ◽  
Stress Analysis ◽  
Mechanical Stress ◽  
Printed Circuit Board ◽  
Organic Substrate ◽  
Circuit Board ◽  
Bottom Surface ◽  
Mechanical Shock ◽  
Analysis And Evaluation ◽  
Pcb Assembly

Recent industry trends to continue enabling increased server system performance and packaging density has driven the need to implement larger form factor hybrid land grid array (LGA) attached organic modules. In addition, given the need to package multiple modules on a single printed circuit board (PCB) assembly, PCB cross-sections and their corresponding physical properties (e.g., flatness, etc.) as well as module bottom surface metallurgy (BSM) co-planarity require a more detailed understanding of impacts to the compliant as well as the soldered connector interfaces. Lastly, the migration to lead (Pb)-free solders has further complicated the issue given both the change in material properties as well as processing temperatures. In this paper we will discuss the mechanical stress analysis and evaluation tests assessment of a recently developed 50 mm square organic processor module, hybrid LGA attached to a multiple site PCB. The analysis presented will highlight the methodology to identify both connector soldered stress and predicted contact load variation across the module's mated interface. Key parameters discuss will include the PCB flatness, Organic substrate BSM co-planarity (both predicted and measured) and the Hybrid LGA as-soldered contact co-planarity. Corroborating predicted analytical results, we will discuss various evaluation tests performed to validate the design's integrity. Key tests include, pressure sensitive film (PSF) studies and environment stress exposures, including thermal shock, mechanical shock and vibration and seismic exposure. Post test electrical integrity and test sample construction analysis, including 3D x-ray and mechanical cross-section, will also be described. The analysis process and testing described will provide a method to evaluate more challenging hybrid LGA applications as both module sizes and/or number applied per PCB assembly increase and Pb-free assembly is introduced in future applications.

A Novel Discrete Passives Integration on Organic Substrate

2005 ◽  
Author(s):  
Vasudivan Sunappan ◽  
Chee Wai Lu ◽  
Lai Lai Wai ◽  
Wei Fan ◽  
Boon Keng Lok
Keyword(s):  
Integrated Circuits ◽  
Printed Circuit Board ◽  
Organic Substrate ◽  
Temperature Cycling ◽  
Circuit Board ◽  
Electrical Performance ◽  
Core Material ◽  
Bottom Surface ◽  
Passive Components ◽  
Printed Circuit

A novel process has been developed to embed discrete (surface mountable) passive components like capacitors, resistors and inductors using printed circuit board fabrication technology. The process comprises of mounting passive components on top surface of a core PCB (printed circuit board) material using surface mount technology. The passive components mounting were designed in multiple clusters within the PCB. Dielectric sheets are sandwiched between top surface of core PCB and second PCB material for lamination process. A direct interconnection of the passive components to one or more integrated circuits (IC) is further accomplished by mounting the ICs on the bottom surface of the core material in an area directly under the passive components. The close proximity of the embedded passive components such as capacitors to an IC improved electrical performance by providing impedance reduction and resonance suppression at high frequency range. The reliability of solder joints was evaluatedd by temperature cycling test.

Nonlinear-Time-Dependent Analysis of Micro Via-In-Pad Substrates for Solder Bumped Flip Chip Applications

2002 ◽  
Vol 124 (3) ◽  
pp. 205-211 ◽  
Author(s):  
John H. Lau ◽  
S. W. Ricky Lee ◽  
Stephen H. Pan ◽  
Chris Chang
Keyword(s):  
Cross Sections ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Low Cost ◽  
Circuit Board ◽  
Test Results ◽  
Pcb Assembly ◽  
Creep Analysis ◽  
Chip Scale Package ◽  
Time Dependent Analysis

An elasto-plastic-creep analysis of a low-cost micro via-in-pad (VIP) substrate for supporting a solder bumped flip chip in a chip scale package (CSP) format which is soldered onto a printed circuit board (PCB) is presented in this study. Emphasis is placed on the design, materials, and reliability of the micro VIP substrate and of the micro VIP CSP solder joints on PCB. The solder is assumed to obey Norton’s creep law. Cross-sections of samples are examined for a better understanding of the solder bump, CSP substrate redistribution, micro VIP, and solder joint. Also, the thermal cycling test results of the micro VIP CSP PCB assembly is presented.

Origami for Tight Spaces - 3D 250C PCB Assemblies for Control Systems

2019 ◽  
Vol 2019 (HiTen) ◽  
pp. 000034-000038 ◽  
Author(s):  
Piers Tremlett ◽  
Phil Elliot ◽  
Pablo Tena
Keyword(s):  
High Temperature ◽  
Printed Circuit Board ◽  
Real Life ◽  
Circuit Board ◽  
Calibration Data ◽  
Engine Fuel ◽  
Sensors And Actuators ◽  
Pcb Assembly ◽  
Operational Life ◽  
Mems Technology

Printed circuit board (PCB) assemblies must fit into unusual spaces for many real-life, high temperature applications such as sensors and actuators. This paper details the design and manufacture of a complex control circuit for a jet engine fuel flow valve. “Origami” was needed to fit this control circuitry into the tight space in the valve, this was achieved using a high temperature flex rigid PCB assembly. The valve was mounted on a hot section of the engine, and the assembly was tested for its capability to operate at 178°C and withstand multiple thermal cycles of −55°C and 175°C during its operational life. Various component joining media were investigated to extend the life of the assembly. The project also developed a one-time programmable (OTP) memory aimed at up to 300°C operation for on board memory to provide calibration data or boot memory for high temperature microcontrollers or processors. The device was based on Micro-Electro-Mechanical Systems (MEMS) technology.

Pretreatment of Blind Via Holes before Ni/Au and Cu Plating Applied with Atmospheric Pressure Plasma Jet

2005 ◽  
Vol 2 (3) ◽  
pp. 189-196 ◽  
Author(s):  
Yasushi Sawada ◽  
Keiichi Yamazaki ◽  
Noriyuki Taguchi ◽  
Tetsuji Shibata
Keyword(s):  
Atmospheric Pressure ◽  
Printed Circuit Board ◽  
Formation Rate ◽  
Plasma Processing ◽  
Atmospheric Pressure Plasma ◽  
Plasma Jet ◽  
Circuit Board ◽  
Bottom Surface ◽  
Printed Circuit ◽  
Via Holes

The effectiveness of atmospheric pressure (AP) plasma preprocessing before Ni/Au or Cu plating has been examined by applying it to a build-up printed circuit board (FR-4 grade) and polyimide-based flexible circuit film, both with blind via-holes (BVHs). The AP plasma applied with a dielectric barrier discharge is generated inside a 56 mm wide quartz vessel by an RF power generator using Ar-O2 gas mixture. One side of the vessel is open and the plasma jet is blown on the sample substrate transported 5 mm downward from the outlet of the vessel. The deposit failure rate of Ni/Au electroless deposit to 50 μm-diameter BVHs formed on a photo resist on the printed circuit board is 12.5% without preprocessing but is decreased to 0% after applying the AP plasma processing. As for 50 μm-diameter BVHs formed with a YAG laser on a polyimide-based flexible circuit film, the bump formation using electrolytic copper plating fails without preprocessing, but a 100% bump formation rate is achieved after applying AP plasma processing. It is presumed that the AP plasma processing improves the wetting property of the BVH walls and allows the plating solution to uniformly cover the entire wall surfaces without generating bubbles. The removal of organic substances attached to the BVH bottom surface also helps to improve the adherence of metal plating.

I/O Printed Circuit Board Assemblies; Recent Learning in Mechanical Stress Analysis, Verification Testing, and Post-test Analysis Techniques and Results

2015 ◽  
Vol 2015 (1) ◽  
pp. 000169-000178
Author(s):  
John Torok ◽  
Shawn Canfield ◽  
Suraush Khambati ◽  
Robert Mullady ◽  
Budy Notohardjono ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Measurement Techniques ◽  
Form Factors ◽  
Mechanical Analysis ◽  
Circuit Board ◽  
Mechanical Shock ◽  
Test Analysis ◽  
Printed Circuit ◽  
Analysis Techniques ◽  
Post Test

Recent high-end server designs have included new Input / Output (I/O) printed circuit board (PCB) assemblies consisting of a variety of form factors, electronic design layouts, and packaging assembly characteristics. To insure the required functional and reliability aspects are established and maintained, new mechanical analysis and verification testing techniques have been recently devised. A description of the design application set, the analysis tools and techniques applied, and the verification testing completed, including the associated measurement techniques as well as post-testing analysis methods and results are presented. Also included are the recent PCB raw card characterization efforts whose results have been applied as material property inputs to the analysis to improve analytical-to-empirical correlation. Included within the application set are both the use of custom designed cards as well as industry standard, original equipment manufacturer (OEM) cards that are packaged within custom enclosures. Given packaged and unpackaged (i.e., as installed in a higher-level rack system assembly) fragility testing requirements, new analysis techniques exploiting the capabilities of LS-DYNA have been used to provide a predictive means to support both initial as well as iterative design levels. In addition, these analysis results are also used to identify locations for measurement sensor placement employed during mechanical verification testing. Thermal shock and mechanical shock and vibration verification testing details and results are provided describing the conditions applied to simulate assembly shipping conditions, both as packaged as well as in situ to the higher-level of assembly. Included with this is a discussion with respect to post-test analysis techniques and results, including the use of both microscopic cross-section analysis as well as dye-pry assessments. Concluding, continued and future activities are described as “best practices” for the application of this methodology as part of the end-to-end development process.

Modeling of Errors Counting System for PCB Soldered in the Wave Soldering Technology

2014 ◽  
Vol 874 ◽  
pp. 139-143 ◽  
Author(s):  
Jacek Pietraszek ◽  
Aneta Gądek-Moszczak ◽  
Tomasz Toruński
Keyword(s):  
Quality Assurance ◽  
Experimental Design ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Counting System ◽  
Printed Circuit ◽  
Pcb Assembly ◽  
Wave Soldering ◽  
Soldering Technology ◽  
Through Hole

PartnerTech provides printed circuit board (PCB) assembly on request. Wired elements are assembled in through-hole technology and soldered on the wave soldering machine. The PCB with inserted elements is passed across the pumped wave of melted solder. Typically this process is accompanied by some class of defects like cracks, cavities, wrong solder thickness and poor conductor. In PartnerTech Ltd. another type of defects was observed: dispersion of small droplets of solder around holes. Quality assurance department plans to optimize the process in order to reduce the number of defects. In the first stage, it was necessary to develop a methodology for counting defects. This paper presents experimental design and analysis related to this project.

A Virtual Prototyping Framework for Electronics Manufacturing

Manufacturing ◽  
2002 ◽  
Author(s):  
J. Cecil ◽  
A. Kanchanapiboon
Keyword(s):  
Life Cycle ◽  
Printed Circuit Board ◽  
Virtual Prototyping ◽  
Circuit Board ◽  
Electronics Manufacturing ◽  
Functional Evaluation ◽  
Surface Mount Technology ◽  
Team Members ◽  
Printed Circuit ◽  
Pcb Assembly

This paper presents a framework for supporting virtual prototyping related activities in the domain of printed circuit board (PCB) assembly. The focus of discussion is restricted to Surface Mount Technology (SMT) based processes only. In general, Virtual Prototyping enables the conceptualization, evaluation and validation of proposed ideas, plans and solutions. Using a virtual prototyping framework, cross functional evaluation and analysis can be facilitated where designers, manufacturing engineers, testing and other life-cycle team members can communicate effectively as well as identify and eliminate problems, which may arise later in the downstream manufacturing and testing activities.

A Computable Model for PCB Assembly Optimization Based on Polychromatic Sets

2013 ◽  
Vol 470 ◽  
pp. 173-176
Author(s):  
Xuan Du ◽  
Gang Yu
Keyword(s):  
Printed Circuit Board ◽  
Resource Constraints ◽  
Optimization Problems ◽  
Circuit Board ◽  
Computable Model ◽  
Model Framework ◽  
Pcb Assembly ◽  
Modeling Methodology ◽  
Machine Failure ◽  
Order Change

A modeling methodology is presented for printed circuit board(PCB) assembly optimization based on polychromatic sets(PS) theory. A computable model framework with hierarchical structure includes three layers, which are set layer(SL), logic layer(LL) and numerical layer(NL). Based on the hierarchical model and the mapping relationship among each layer, a computable model is formulated to describe the PCB assembly optimization problem in multiple PCB assembly tasks and multiple machines. The computable model not only involves various computation parameters, complicate constraint relationships such as process constraints, resource constraints and so on in PCB assembly optimization, but also describes the shortage of component, machine failure, order change and other uncertain factors. The optimization problems of PCB assembly in low-volume environment and multiple tasks can be solved efficiently.

Planning of Component Placement/Insertion Sequence and Feeder Setup in PCB Assembly Using Genetic Algorithm

1993 ◽  
Vol 115 (4) ◽  
pp. 424-432 ◽  
Author(s):  
M. C. Leu ◽  
H. Wong ◽  
Z. Ji
Keyword(s):  
Genetic Algorithm ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Assembly Planning ◽  
Genetic Operators ◽  
Printed Circuit Board Assembly ◽  
Component Placement ◽  
Pcb Assembly ◽  
Circuit Board Assembly ◽  
Genetic Algorithm Approach

A new application of the genetic algorithm approach is introduced to solve printed circuit board assembly planning problems. The developed genetic algorithm finds the sequence of component placement/insertion and the arrangement of feeders simultaneously, for achieving the shortest assembly time, for three main types of assembly machines. The algorithm uses links (parents) to represent possible solutions and it applies genetic operators to generate new links (offspring) in an iterative procedure to obtain nearly optimal solutions. Examples are provided to illustrate solutions generated by the algorithm.

Damage and Failures of CGA/BGA Assemblies Under Thermal Cycling and Dynamic Loadings

2013 ◽  
Author(s):  
Reza Ghaffarian
Keyword(s):  
Thermal Cycling ◽  
Mechanical Loading ◽  
Test Data ◽  
Printed Circuit Board ◽  
High Reliability ◽  
Circuit Board ◽  
Design Parameters ◽  
Mechanical Shock ◽  
Space Applications ◽  
High Processing

Commercial-off-the-shelf column/ball grid array packaging (COTS CGA/BGA) technologies in high-reliability versions are now being considered for use in high-reliability electronic systems. For space applications, these packages are prone to early failure due to the severe thermal cycling in ground testing and during flight, mechanical shock and vibration of launch, as well as other less severe conditions, such as mechanical loading during descent, rough terrain mobility, handling, and ground tests. As the density of these packages increases and the size of solder interconnections decreases, susceptibility to thermal, mechanical loading and cycling fatigue grows even more. This paper reviews technology as well as thermo-mechanical reliability of field programmable gate array (FPGA) IC packaging developed to meet demands of high processing powers. The FPGAs that generally come in CGA/PBGA packages now have more than thousands of solder balls/columns under the package area. These packages need not only to be correctly joined onto printed circuit board (PCB) for interfacing; they also should show adequate system reliability for meeting thermo-mechanical requirements of the electronics hardware application. Such reliability test data are rare or none for harsher environmental applications, especially for CGAs having more than a thousand of columns. The paper also presents significant test data gathered under thermal cycling and drop testing for high I/O PBGA/CGA packages assembled onto PCBs. Damage and failures of these assemblies after environmental exposures are presented in detail. Understanding the key design parameters and failure mechanisms under thermal and mechanical conditions is critical to developing an approach that will minimize future failures and will enable low-risk insertion of these advanced electronic packages with high processing power and in-field re-programming capability.

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