scholarly journals Electroless Plating with UV Modification for Thermosetting Dielectric and Decay Suppression of High Frequency Transmission Property

2021 ◽  
Vol 18 (2) ◽  
pp. 51-58
Author(s):  
Masaya Toba ◽  
Kazuyuki Mitsukura ◽  
Masaki Yamaguchi
Keyword(s):  
Surface Roughness ◽  
Seed Layer ◽  
High Performance ◽  
Printed Circuit Boards ◽  
Peel Strength ◽  
Strip Line ◽  
Additive Process ◽  
Anchoring Effect ◽  
Cu Film ◽  
Semiconductor Packages

Abstract Semiconductor packages for high-performance devices with printed circuit boards having multi-wiring layers such as FC-BGA have been attracting attention to realize ultrareliable and low-latency communications in 5G networking. Cu wirings for the package are usually fabricated by the semi-additive process (SAP) with the de-smear process and/or the modified semi-additive process (MSAP) by using Cu film with large surface roughness. Although a de-smear process and Cu film can obtain enough adhesion between dielectric and Cu seed layer by the anchoring effect to secure reliabilities, the interface between dielectric and Cu seed layer should be smooth to achieve low attenuation of electric signals at high frequencies. Here, instead of those processes, we applied UV modification for the surface of our developed thermosetting dielectric to realize a smooth and high-adhesive seed layer against the dielectric. We obtained .5 kN/m of peel strength between dielectric and Cu seed layer despite surface roughness (Ra) of dielectric being 265 nm by the nano-level anchoring effect at UV modified layer. Because of the smooth interface by UV modification, the normalized S21 value of micro-strip line was about 29% improved compared with that assembled through Cu film with Ra of 2,400 nm at 50 GHz.

Electroless Plating with UV Modification for Thermosetting Dielectric and Decay Suppression of High Frequency Transmission Property

2020 ◽  
Vol 2020 (1) ◽  
pp. 000174-000180
Author(s):  
Masaya Toba ◽  
Kazuyuki Mitsukura ◽  
Masaki Yamaguchi
Keyword(s):  
Surface Roughness ◽  
Seed Layer ◽  
High Performance ◽  
Printed Circuit Boards ◽  
Peel Strength ◽  
Circuit Boards ◽  
Additive Process ◽  
Anchoring Effect ◽  
Cu Film ◽  
Semiconductor Packages

Abstract Semiconductor packages for high performance devices with printed circuit boards having multi wiring layers such as FC-BGA have been attracting the attention in order to realize ultra-reliable and low latency communications in 5G networking. Cu wirings for the package are usually fabricated by semi-additive process (SAP) with desmear process and/or modified semi-additive process (MSAP) by using Cu film with large surface roughness. Though a desmear process and Cu film can obtain enough adhesion between dielectric and Cu seed layer by anchoring effect to secure reliabilities, the interface between dielectric and Cu seed layer should be smooth to achieve low attenuation of electric signals at high frequencies. Here, instead of that processes, we applied an UV modification for the surface of our developed thermosetting dielectric in order to realize a smooth and high adhesive seed layer against the dielectric. We obtained 0.5 kN/m of peel strength between dielectric and Cu seed layer in spite of surface roughness (Ra) of dielectric was 265 nm by nano-level anchoring effect at UV modified layer. Due to the smooth interface by UV modification, the normalized S21 value of microstrip line was about 29 % improved compared to that assembled through Cu film with Ra of 2400 nm at 50 GHz.

Semi-additive Process Based Cu Wirings with Ultra Smooth Electroless Cu Seed Layer and Important Factor for High Frequency Transmission Property

2019 ◽  
Vol 2019 (1) ◽  
pp. 000409-000414
Author(s):  
Masaya Toba ◽  
Shuji Nomoto ◽  
Nobuhito Komuro ◽  
Kazuyuki Mitsukura ◽  
Shinichiro Abe ◽  
...  
Keyword(s):  
Seed Layer ◽  
High Performance ◽  
Printed Circuit Boards ◽  
Peel Strength ◽  
60 Ghz ◽  
Circuit Boards ◽  
Additive Process ◽  
Seed Formation ◽  
Anchoring Effect ◽  
Semiconductor Packages

Abstract Semiconductor packages for high performance devices with printed circuit boards having multi wiring layers such as FC-BGA have been attracting the attention in order to realize ultra-reliable and low latency communications in 5G networking. Cu wirings for the package are usually fabricated by via formation by laser for dielectric, desmear, electroless Cu seed formation, photoresist patterning, electrolytic Cu plating, resist stripping and seed layer etching. Though a desmear process can obtain enough adhesion between dielectric and Cu seed layer by anchoring effect to secure reliabilities, the interface between dielectric and Cu seed layer should be smooth to achieve low attenuation of electric signals at high frequencies. Here, instead of a desmear process, we applied an UV modification for the surface of dielectric in order to realize a smooth and high adhesive seed layer against dielectric. We obtained 0.8 kN/m of peel strength between dielectric and Cu seed layer in spite of surface roughness (Ra) of dielectric was 45 nm by nano-level anchoring effect at UV modified layer. Due to the smooth interface by UV modification, S21 value of microstrip line was 26 % improved compared to that assembled through desmear process at 60 GHz.

scholarly journals Assembly of Cu Wirings with Ultrasmooth and High-Adhesive Electroless Cu Seed Layer by Using UV Modification and Low Attenuation of High-Frequency Transmission Property

2020 ◽  
Vol 17 (2) ◽  
pp. 45-51
Author(s):  
Masaya Toba ◽  
Shuji Nomoto ◽  
Nobuhito Komuro ◽  
Kazuyuki Mitsukura ◽  
Shinichiro Abe ◽  
...  
Keyword(s):  
Seed Layer ◽  
High Performance ◽  
Flip Chip ◽  
Printed Circuit Boards ◽  
Peel Strength ◽  
60 Ghz ◽  
Circuit Boards ◽  
Seed Formation ◽  
Anchoring Effect ◽  
Semiconductor Packages

Abstract Semiconductor packages for high-performance devices with printed circuit boards having multiwiring layers such as flip-chip ball grid array have been attracting the attention to realize ultrare-liable and low-latency communications in 5G networking. Cu wirings for the package are usually fabricated by via formation by laser for dielectric, desmear, electroless Cu seed formation, photoresist patterning, electrolytic Cu plating, resist stripping, and seed layer etching. Although a desmear process can obtain enough adhesion between dielectric and Cu seed layer by anchoring effect to secure reliabilities, the interface between dielectric and Cu seed layer should be smooth to achieve low attenuation of electric signals at high frequencies. Here, instead of a desmear process, we applied a UV modification for the surface of dielectric to realize a smooth and high-adhesive seed layer against dielectric. We obtained .8 kN/m of peel strength between dielectric and Cu seed layer in spite of surface roughness of the dielectric being 45 nm by a nanolevel anchoring effect at the UV-modified layer. Because of the smooth interface by UV modification, the S21 value of microstrip line was 26% improved compared with that assembled through the desmear process at 60 GHz.

Advanced Build-up Materials for High Speed Transmission Application

2018 ◽  
Vol 2018 (1) ◽  
pp. 000305-000309 ◽  
Author(s):  
Shiro Tatsumi ◽  
Shohei Fujishima ◽  
Hiroyuki Sakauchi
Keyword(s):  
High Speed ◽  
Printed Circuit Boards ◽  
Transmission Loss ◽  
Coefficient Of Thermal Expansion ◽  
Strip Line ◽  
Circuit Boards ◽  
Additive Process ◽  
Printed Circuit ◽  
Low Dielectric ◽  
Transmission Speed

Abstract Build-up process is a highly effective method for miniaturization and high density integration of printed circuit boards. Along with increasing demands for high transmission speed of electronic devices with high functionality, packaging substrates installed with semiconductors in such devices are strongly required to reduce the transmission loss. Our insulation materials are used in a semi-additive process (SAP) with low dielectric loss tangent, smooth resin surface after desmear, and good insulation reliability. Actually, the transmission loss of strip line substrates and Cu surface roughness impact on transmission loss were measured using our materials. Furthermore, low dielectric molding film with low coefficient of thermal expansion (CTE) and low Young's modulus are introduced.

Method to Measure Effects of Surface Roughness on High-frequency Transmission Lines

2013 ◽  
Vol 2013 (1) ◽  
pp. 000496-000499
Author(s):  
Toshiki Iwai ◽  
Daisuke Mizutani ◽  
Motoaki Tani
Keyword(s):  
Surface Roughness ◽  
Transmission Lines ◽  
Printed Circuit Boards ◽  
Skin Depth ◽  
Capacitive Coupling ◽  
Strip Line ◽  
Circuit Boards ◽  
Three Samples ◽  
Novel Method ◽  
Effect Of Surface

In recent years, the transmission losses induced by surface roughness of conductors in printed circuit boards (PCB) have become important from the standpoint of signal integrity. To clarify this effect, current measurement methods use a microstrip line or a strip line in the PCB, which is fabricated for different values of surface roughness. However, since errors are induced in each sample because of the presence of dispersion in the manufacturing process, it is difficult to extract the effect of surface roughness from the measured data. In this paper, we propose a novel method to measure the effect by means of using capacitive coupling in which the dispersion errors can be eliminated. The results have been verified using electromagnetic simulation. This method was performed on three samples having differing values of surface roughness. It was concluded that the transmission characteristics are influenced by surface roughness at higher frequencies when the skin depth becomes comparable to the surface roughness.

Ultra-smooth and robust graphene-based hybrid anode for high-performance flexible organic light-emitting diodes

2021 ◽  
Author(s):  
zhikun zhang ◽  
lianlian xia ◽  
Lizhao Liu ◽  
Yuwen Chen ◽  
zuozhi wang ◽  
...  
Keyword(s):  
Surface Roughness ◽  
Chemical Vapor Deposition ◽  
Vapor Deposition ◽  
High Performance ◽  
Light Emitting Diodes ◽  
Chemical Vapor ◽  
Organic Light Emitting Diodes ◽  
Light Emitting ◽  
Organic Light ◽  
Large Particles

Large surface roughness, especially caused by the large particles generated during both the transfer and the doping processes of graphene grown by chemical vapor deposition (CVD) is always a critical...

scholarly journals 27.2: Invited Paper: Towards High Performance Gate Electrodes: Resistance Reduction in Molybdenum Films by Seed Layer Application

2021 ◽  
Vol 52 (S1) ◽  
pp. 170-174
Author(s):  
Hennrik Schmidt ◽  
Harald Koestenbauer ◽  
Dominik Lorenz ◽  
Christian Linke ◽  
Enrico Franzke ◽  
...  
Keyword(s):  
Seed Layer ◽  
High Performance ◽  
Gate Electrodes ◽  
Resistance Reduction

scholarly journals Effects of LaNiO3 Seed Layer on the Microstructure and Electrical Properties of Ferroelectric BZT/PZT/BZT Thin Films

2021 ◽  
Vol 8 ◽  
Author(s):  
Jinyu Ruan ◽  
Chao Yin ◽  
Tiandong Zhang ◽  
Hao Pan
Keyword(s):  
Thin Film ◽  
Thin Films ◽  
Surface Roughness ◽  
Electrical Properties ◽  
Seed Layer ◽  
Ferroelectric Properties ◽  
Lower Surface ◽  
Multilayer Films ◽  
Multilayer Thin Films ◽  
Orientation Growth

Ferroelectric multilayer films attract great attention for a wide variation of applications. The synergistic effect by combining different functional layers induces distinctive electrical properties. In this study, ferroelectric BaZr0.2Ti0.8O3/PbZr0.52Ti0.48O3/BaZr0.2Ti0.8O3 (BZT/PZT/BZT) multilayer thin films are designed and fabricated by using the magnetron sputtering method, and a LaNiO3 (LNO) seed layer is introduced. The microstructures and electrical properties of the BZT/PZT/BZT films with and without the LNO seed layer are systematically studied. The results show that the BZT/PZT/BZT/LNO thin film exhibits much lower surface roughness and a preferred (100)-orientation growth, with the growth template and tensile stress provided by the LNO layer. Moreover, an enhanced dielectric constant, decreased dielectric loss, and improved ferroelectric properties are achieved in BZT/PZT/BZT/LNO thin films. This work reveals that the seed layer can play an important role in improving the microstructure and properties of ferroelectric multilayer films.

Process and Evaluation of High Reliability Reworkable Edge Bond Adhesives for Large Area BGA Applications

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 002018-002053
Author(s):  
Swapan Bhattacharya ◽  
Fei Xie ◽  
Daniel F. Baldwin ◽  
Han Wu ◽  
Kelley Hodge ◽  
...  
Keyword(s):  
High Performance ◽  
Printed Circuit Boards ◽  
Process Development ◽  
High Reliability ◽  
Optimum Process ◽  
Process Conditions ◽  
Harsh Environment ◽  
Mechanical Shock ◽  
Large Area ◽  
Reliability Performance

Reworkable underfills and edge bond adhesives are finding increasing utility in high reliability and harsh environment applications. The ASICs and FPGAs often used in these systems typically require designs incorporating large BGAs and ceramic BGAs. For these high reliability and harsh environment applications, these packages typically require underfill or edge bond materials to achieve the needed thermal cycle, mechanical shock and vibration reliability. Moreover, these applications often incorporate high dollar value printed circuit boards (on the order of thousands or tens of thousands of dollars per PCB) hence the need to rework these assemblies and maintain the integrity of the PCB and high dollar value BGAs. This further complicates the underfill requirements with a reworkability component. Reworkable underfills introduce a number of process issues that can result in significant variability in reliability performance. In contrast, edge bond adhesives provide a high reliability solution with substantial benefits over underfills. One interesting question for the large area BGA applications of reworkable underfills and edge bond materials is the comparison of their reliability performance. This paper presents a study of reliability comparison between two robust selected reworkable underfill and edge bond adhesive in a test vehicle including 11mm, 13mm, and 27mm large area BGAs. Process development for those large area BGA applications was also conducted on the underfill process and edge bond process to determine optimum process conditions. For underfill processing, establishing an underfill process that minimizing/eliminates underfill voids is critical. For edge bond processing, establishing an edge bond that maximizes bond area without encapsulating the solder balls is key to achieving high reliability. In addition, this paper also presents a study of new high performance reworkable edge bond materials designed to improve the reliability of large area BGAs and ceramic BGAs assemblies while maintaining good reworkablity. Four edge bond materials (commercially available) were studied and compared for a test vehicles with 12mm BGAs. The reliability testing protocol included board level thermal cycling (−40 to 125°C), mechanical drop testing (2900 G), and random vibration testing (3 G, 10 – 1000 Hz).

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