Integrated Protection Circuits for an NMOS Silicon Carbide Gate Driver Integrated Circuit

2014 ◽  
Vol 2014 (HITEC) ◽  
pp. 000218-000223 ◽  
Author(s):  
Paul Shepherd ◽  
Dillon Kaiser ◽  
Michael Glover ◽  
Sonia Perez ◽  
A. Matt Francis ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Integrated Circuit ◽  
Leading Edge ◽  
Power Supplies ◽  
Power Device ◽  
Bench Test ◽  
Test Results ◽  
Detection Circuit ◽  
Gate Driver ◽  
Protection Circuits

Recent work has been done to build a Silicon Carbide (SiC) gate driver IC for use with a 1,200V SiC power MOSFET. Protection circuits form an important part of the complete gate driver/power device system. Under-voltage lockout (UVLO) protection disables the gate driver when power supplies are insufficient to turn the power device fully on. Desaturation detection provides protection to the power device by recognizing over-current conditions and disabling the gate driver for a set duration. The protection circuits described in this paper are integrated with a novel SiC gate-driver architecture utilizing discrete 20 V and 40 V power supplies. Two separate UVLO circuits monitor these power supplies while being powered by the 20 V supply. The desaturation detection circuit ensures that the power device is in its safe operating area. The desaturation detection circuit is designed to work with a 20A SiC MOSFET in less than 500ns, while avoiding false triggering on leading-edge spikes. Bench test results of the two UVLOs and desaturation detection circuits were captured and are compared to simulated results.

Operation of Silicon Carbide Integrated Circuits under High Temperature and Pressure

2017 ◽  
Vol 2017 (1) ◽  
pp. 000526-000530
Author(s):  
M. Barlow ◽  
A. M. Francis ◽  
J. Holmes
Keyword(s):  
Silicon Carbide ◽  
High Pressure ◽  
High Temperature ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Leading Edge ◽  
Limited Information ◽  
High Temperature And Pressure ◽  
Temperature And Pressure

Abstract Silicon carbide integrated circuits have demonstrated the ability to function at temperatures as high as 600 °C for extended periods of time. Many environments where high temperature in-situ electronics are desired also have large pressures as well. While some validation has been done for high pressure environments, limited information on the parametric impact of pressure on SiC integrated circuits is available. This paper takes two leading-edge SiC integrated circuit processes using two different classes of devices (JFET and CMOS), and measures the performance through temperature and pressure variation. Circuit functionality was verified at high temperature (475 °C) as well as high pressure (1700 psig).

scholarly journals Investigation on a Novel Capacitive Electrode for Geophysical Surveys

2016 ◽  
Vol 2016 ◽  
pp. 1-9 ◽  
Author(s):  
Zhiyu Wang ◽  
Shun Wang ◽  
Guangyou Fang ◽  
Qunying Zhang
Keyword(s):  
Electrical Contact ◽  
Capacitive Coupling ◽  
Environmental Damage ◽  
Good Prospect ◽  
Test Results ◽  
Geophysical Surveys ◽  
Detection Circuit ◽  
Operating Bandwidth ◽  
Capacitive Electrode ◽  
Alternative Structure

Nonpolarizable electrodes are applied widely in the electric field measurement for geophysical surveys. However, there are two major problems: (1) systematic errors caused by poor electrical contact in the high resistive terrains and (2) environmental damage associated with using nonpolarizable electrodes. A new alternative structure of capacitive electrode, which is capable of sensing surface potential through weak capacitive coupling, is presented to solve the above problems. A technique is introduced to neutralize distributed capacitance and input capacitance of the detection circuit. With the capacitance neutralization technique, the transmission coefficient of capacitive electrode remains stable when environmental conditions change. The simulation and field test results indicate that the new capacitive electrode has an operating bandwidth range from 0.1 Hz to 1 kHz. The capacitive electrodes have a good prospect of the applications in geophysical prospecting, especially in resistive terrains.

SHEPWM Class-D Amplifier with a Reconfigurable Gate Driver Integrated Circuit

2021 ◽  
Author(s):  
Nueraimaiti Aimaier ◽  
Nam Ly ◽  
Gabriel Nobert ◽  
Yves Blaquiere ◽  
Nicolas Constantin ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Class D Amplifier ◽  
Class D ◽  
Gate Driver

scholarly journals Modelling of Dynamic Properties of Silicon Carbide Junction Field-Effect Transistors (JFETs)

Energies ◽  
2020 ◽  
Vol 13 (1) ◽  
pp. 187 ◽  
Author(s):  
Kamil Bargieł ◽  
Damian Bisewski ◽  
Janusz Zarębski
Keyword(s):  
Silicon Carbide ◽  
Integrated Circuit ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Dynamic Properties ◽  
Modified Model ◽  
Spice Model ◽  
Capacitance Voltage ◽  
Effect Transistor ◽  
Switching Characteristics

The paper deals with the problem of modelling and analyzing the dynamic properties of a Junction Field Effect Transistor (JFET) made of silicon carbide. An examination of the usefulness of the built-in JFET Simulation Program with Integrated Circuit Emphasis (SPICE) model was performed. A modified model of silicon carbide JFET was proposed to increase modelling accuracy. An evaluation of the accuracy of the modified model was performed by comparison of the measured and calculated capacitance–voltage characteristics as well as the switching characteristics of JFETs.

scholarly journals A special high-frequency soft-switched DC/DC power supply for GCT gate driver

2021 ◽  
Author(s):  
Jahangir Afsharian
Keyword(s):  
Power Supply ◽  
High Frequency ◽  
Optimization Procedure ◽  
Power Supplies ◽  
Zero Voltage Switching ◽  
General Power ◽  
Gate Driver ◽  
Isolation Transformer ◽  
Experimental Use ◽  
Gate Drivers

This thesis is devoted to the development of a novel parallel isolated power supply (PIPS) for the gate driver of integrated Gate Commutated Thyristors (GCT). The proposed PIPS is essentially a special high frequency soft switched DC/DC converter, integrating six parallel isolated power supplies in one module where each power supply generates a regulated dc supply for the GCT gate driver. In commercial GCT power supplies, a high-voltage isolation transformer is indispensable but highly inefficient in terms of cost and size, which can be significantly improved by the optimized transformer. In all, this design strives to achieve a general power supply for powering up the gate drivers of all types of GCT devices in all MV applications with minimal changes in configuration. In this thesis, the configuration of PIPS is presented and its operating principle is elaborated. The transformer optimization procedure satisfying the voltage isolation requirement of GCT gate drivers is extensively discussed. The performance of PIPS, including the front end DC/DC converter, zero voltage switching phase-shift full bridge (ZVS-PS-FB) converter, and the optimization of the transformer, is verified by simulations and experiments where a 360W laboratory prototype is built for the experimental use.

scholarly journals Performance evaluation of GaN and Si based driver circuits for a SiC MOSFET power switch

2021 ◽  
Vol 12 (3) ◽  
pp. 1293
Author(s):  
Martin J. Carra ◽  
Hernan Tacc ◽  
Jose Lipovetzky
Keyword(s):  
Silicon Carbide ◽  
Performance Evaluation ◽  
Gallium Nitride ◽  
Switching Process ◽  
Control Power ◽  
Power Switch ◽  
Power Switches ◽  
Gate Driver ◽  
Output Losses

<p>Silicon Carbide (SiC), new power switches (PSW) require new driver circuits which can take advantage of their new capabilities. In this paper a novel Gallium Nitride (GaN) based gate driver is proposed as a solution to control SiC power switches. The proposed driver is implemented and is performance compared with its silicon (Si) counterparts on a hard switching environment. A thorough evaluation of the energy involved in the switching process is presented showing that the GaN based circuit exhibits similar output losses but reduces the control power needed to operate at a specified frequency.</p>

Simulation Analysis of the Working Process of the Corn Seed Metering Device with Combination Inner-Cell

2012 ◽  
Vol 215-216 ◽  
pp. 160-167 ◽  
Author(s):  
Qing Long Li ◽  
Ji Yang Yu ◽  
Qiang Qiang Zhang ◽  
Jian Qun Yu ◽  
Hong Fu
Keyword(s):  
Simulation Analysis ◽  
Three Dimensional ◽  
Bench Test ◽  
Particle Model ◽  
Test Results ◽  
Working Process ◽  
Corn Seed ◽  
3D Cad ◽  
Novel Method ◽  
Seed Metering Device

A three-dimensional discrete element method analytic model of the corn seed metering device with combination inner-cell was established based on its 3D CAD model, and the three-dimensional particle model of corn seeds was built by using the method of combination spherical particle. The working process of the corn seed metering device was simulated and analyzed by self-developed three-dimensional CAE software. It was observed that the simulative results of the seeding performance, clearing angles and dropping angles of the corn seeds well agreed with the bench test results. A novel method for studying and designing of the corn seed metering device was put forward.

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