Optimized cavities for microwave applications using the new low loss LTCC material Du Pont 9k7

2012 ◽  
Vol 2012 (CICMT) ◽  
pp. 000258-000262
Author(s):  
Alexander Schulz ◽  
Tilo Welker ◽  
Nam Gutzeit ◽  
Dirk Stoepel ◽  
Frank Wollenschlaeger ◽  
...  

This paper presents two different novel methods to manufacture optimized cavity structures, which are suitable for multilayer System-in-Package (SiP) and Multi-Chip-Module (MCM) applications, in the new low temperature cofired ceramic (LTCC) material Du Pont 9k7. In contrast to standard manufacturing, the improved DP 9k7 cavities show almost perfectly orthogonal cross sections and straight edges, achieved by applying special cavity inlays or cast silicone. Ball-wedge bond wires and wedge-wedge ribbons are implemented directly to the cavity rim successfully. Therefore, these cavities are suitable for very short bond wires in complex RF systems and the introduced techniques are very promising for future applications using DP 9k7.

Author(s):  
Carl Nail

Abstract To overcome the obstacles in preparing high-precision cross-sections of 'blind' bond wires in integrated circuits, this article proposes a different technique that generates reliable, repeatable cross-sections of bond wires across most or all of their lengths, allowing unencumbered and relatively artifact-free analysis of a given bond wire. The basic method for cross-sectioning a 'blind' bond wire involves radiographic analysis of the sample and metallographic preparation of the sample to the plane of interest. This is followed by tracking the exact location of the plane on the original radiograph using a stereomicroscope and finally darkfield imaging in which the wire is clearly visible with good resolution.


2011 ◽  
Vol 324 ◽  
pp. 437-440
Author(s):  
Raed Amro

There is a demand for higher junction temperatures in power devices, but the existing packaging technology is limiting the power cycling capability if the junction temperature is increased. Limiting factors are solder interconnections and bond wires. With Replacing the chip-substrate soldering by low temperature joining technique, the power cycling capability of power modules can be increased widely. Replacing also the bond wires and using a double-sided low temperature joining technique, a further significant increase in the life-time of power devices is achieved.


2019 ◽  
Vol 45 (4) ◽  
pp. 4316-4321 ◽  
Author(s):  
Mahender C ◽  
Sumangala T P ◽  
Ramesh Ade ◽  
Saranya A ◽  
Shiva Prasad ◽  
...  

ChemInform ◽  
2015 ◽  
Vol 46 (43) ◽  
pp. no-no
Author(s):  
Raz Muhammad ◽  
Yaseen Iqbal ◽  
Ian M. Reaney

2018 ◽  
Vol 363 (3) ◽  
Author(s):  
Théophile Tchakoua ◽  
Mama Pamboundom ◽  
Berthelot Said Duvalier Ramlina Vamhindi ◽  
Serge Guy Nana Engo ◽  
Ousmanou Motapon ◽  
...  

2018 ◽  
Vol 47 (11) ◽  
pp. 6383-6389 ◽  
Author(s):  
Chunchun Li ◽  
Huaicheng Xiang ◽  
Changzhi Yin ◽  
Ying Tang ◽  
Yuncui Li ◽  
...  

2010 ◽  
Vol 2010 (1) ◽  
pp. 000028-000035 ◽  
Author(s):  
Jason D. Reed ◽  
Matthew Lueck ◽  
Chris Gregory ◽  
Alan Huffman ◽  
John M. Lannon ◽  
...  

The results of bonding and stress testing of Cu/Sn-Cu bonded dice and Cu-Cu thermocompression bonded dice at 10μm and 15μm pitch in large area arrays are shown. The interconnect bonding process pressure and temperature required for the formation of low resistance (<100 mΩ), high yielding (99.99 % individual bond yield), and reliable interconnects is described. In the case of Cu/Sn-Cu, use of a mechanical key was found to improve yield. A run of 22 consecutive bond pairs was made with the mechanical key, resulting in 98 % aggregate channel yield at 10μm pitch in area arrays containing 325,632 individual bonds per die to achieve an interconnect density of 106 / cm2. SEM cross sections of Cu/Sn-Cu and Cu-Cu bonded samples and EDS analysis of Cu/Sn intermetallic compounds both before and after stress testing are presented. The results of thermal cycling and humidity-temperature testing on electrical yield and resistance are presented for Cu/Sn-Cu with underfill. Comparison of the electrical and shear test performance of Cu/Sn-Cu and Cu-Cu is made. Low temperature bonding (at 210°C, below the melting point of tin) is demonstrated to produce high electrical yield, high shear strength and similar intermetallic compound formation to devices bonded at 300°C. The low temperature process may prove useful for integrating IC devices that have low thermal budgets.


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